公开(公告)号：US20240130112A1

公开(公告)日：2024-04-18

申请号：US18464475

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Bongsoo KIM ,  Huijung KIM

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/485 ,  H10B12/488

Abstract: Provided is an integrated circuit device including a substrate that has an active region defined by a plurality of device separation regions, a word line on the substrate and arranged in a word line trench that extends in a first horizontal direction, a bit line on the word line and extending in a second horizontal direction orthogonal to the first horizontal direction, a pad on the active region and having a horizontal width that is larger than the active region, and a bit line contact electrically connecting the bit line to the active region, wherein a level of a lowermost surface of the additional pad is at a same vertical level as a level of a lowermost surface of the bit line contact.

公开(公告)号：US20230044856A1

公开(公告)日：2023-02-09

申请号：US17873242

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Kiseok LEE ,  Hui-Jung KIM ,  Yoosang HWANG

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  G11C5/06

Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

公开(公告)号：US20230005924A1

公开(公告)日：2023-01-05

申请号：US17667652

申请日：2022-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Hui-Jung KIM ,  Sangho LEE

IPC: H01L27/108

Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.