公开(公告)号：US20240283411A1

公开(公告)日：2024-08-22

申请号：US18335583

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanru TANG ,  Hou-Shin CHEN ,  Sahana SADAGOPAN ,  Bhupinder SACHDEV ,  Pranav DAYAL

IPC: H03F1/32 ,  H04L27/36 ,  H04W52/08

CPC classification number: H03F1/3258 ,  H04L27/367 ,  H04W52/08 ,  H03F2201/3233

Abstract: Methods and devices are provided in which a processor of a user equipment (UE) combines loop-back signals from a plurality of antenna paths of the UE to generate a combined signal. The loop-back signals are based on a signal transmitted over the antenna paths. The processor determines power amplifier (PA) polynomials based on a comparison of the combined signal to the signal transmitted over the antenna paths. The processor generates a single look-up table (LUT) for the PA polynomials. The processor applies the single LUT to a transmitted signal of the UE to compensate for PA non-linearity

公开(公告)号：US20230353195A1

公开(公告)日：2023-11-02

申请号：US17731251

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanru TANG ,  Pranav DAYAL ,  Hou-Shin CHEN ,  Pritesh VORA ,  Tienyu CHANG ,  Siuchuang Ivan LU ,  Kee-Bong SONG

IPC: H04B7/04 ,  H03F3/24

CPC classification number: H04B7/04 ,  H03F3/245 ,  H04B2001/0416

Abstract: A closed-loop power control (CLPC) system is disclosed that includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes a first power amplifier, a first output power detector configured to detect a first output power level of the first power amplifier, and a first processor configured to determine a first analog gain for a first controller and a first gain for a first digital-to-analog converter based on a first accumulated error between the first output power level and a target Effective Isotropically Radiated Power. A second processor is configured to set a first variable gain of a first variable gain amplifier coupled to an input of the first power amplifier. The CLPC can be configured to control the gain of the first signal path separately or as one signal path.

公开(公告)号：US20230051037A1

公开(公告)日：2023-02-16

申请号：US17903901

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon LEE ,  Pranav DAYAL ,  Kee-Bong SONG

IPC: H04W52/24 ,  H04B17/10 ,  H04B1/40 ,  H04B17/19

Abstract: A method and a closed-loop antenna impedance tuning (CL-AIT) system are provided. An input reflection coefficient is determined. The input reflection coefficient and a threshold value are compared to determine whether the input reflection coefficient is greater than the threshold value. In response to determining that the input reflection coefficient is greater than the threshold value, an optimal tuner code is determined based on a tuner code search algorithm. The optimal tuner code is applied to configure the CL-AIT system.

公开(公告)号：US20200052726A1

公开(公告)日：2020-02-13

申请号：US16656971

申请日：2019-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Liangbin LI ,  Pranav DAYAL ,  Jungwon LEE ,  Gennady FEYGIN

IPC: H04B1/00 ,  H04B3/462

Abstract: Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.