公开(公告)号：USD1016793S1

公开(公告)日：2024-03-05

申请号：US29771800

申请日：2021-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Han Kim ,  Hyun-Keun Son ,  Bum-Soo Park

Abstract: FIG. 1 is a front perspective view of a case for electronic device, showing our new design;
FIG. 2 is a front view thereof;
FIG. 3 is a rear view thereof;
FIG. 4 is a left-side view thereof;
FIG. 5 is a right-side view thereof;
FIG. 6 is a top view thereof;
FIG. 7 is a bottom view thereof;
FIG. 8 is a rear perspective view thereof; and,
FIG. 9 is a cross sectional view taken through line 9-9 of FIG. 2.
Broken lines illustrate portions of the case for electronic device that form no part of the claimed design.

公开(公告)号：US11164838B2

公开(公告)日：2021-11-02

申请号：US16388004

申请日：2019-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Tae Lee ,  Jung Ho Shim ,  Han Kim

IPC: H01L23/00

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

公开(公告)号：US10923464B2

公开(公告)日：2021-02-16

申请号：US16725449

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Tae Lee ,  Han Kim ,  Hyung Joon Kim

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/552 ,  H01L23/427 ,  H01L23/13 ,  H01L23/10 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10

Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first 10 semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated 15 circuit (PMIC).

公开(公告)号：US10886192B2

公开(公告)日：2021-01-05

申请号：US16821305

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hyun Lim ,  Han Kim ,  Yoon Seok Seo ,  Sang Jong Lee

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor package including a core member having a through-hole, a first semiconductor chip disposed in the through-hole and having an active surface with a connection pad disposed thereon, a first encapsulant for encapsulating at least a portion of the first semiconductor chip, and a connection member disposed on the active surface of the first semiconductor chip and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, a second semiconductor package disposed on the first semiconductor package and including a wiring substrate electrically connected to the connection member, at least one second semiconductor chip disposed on the wiring substrate, and a second encapsulant for encapsulating at least a portion of the second semiconductor chip, and a heat dissipation member covering a lateral surface of the second semiconductor package and exposing an upper surface of the second encapsulant.

公开(公告)号：US10770403B2

公开(公告)日：2020-09-08

申请号：US16197764

申请日：2018-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi Ja Han ,  Han Kim ,  Seong Chan Park

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A fan-out semiconductor package includes a connection member including an insulating layer and a redistribution layer, a semiconductor chip disposed on the connection member, an encapsulant encapsulating the semiconductor chip, and an electromagnetic radiation blocking layer disposed above the semiconductor chip and including a base layer in which a plurality of degassing holes are formed and a porous blocking portion filled in the plurality of degassing holes.

公开(公告)号：US10672727B2

公开(公告)日：2020-06-02

申请号：US16108202

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Jung Ho Shim ,  Jun Young Won ,  Han Kim

IPC: H01L23/64 ,  H01L23/552 ,  H01L23/12 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a support member having first and second surfaces opposing each other, having first and second through-holes, spaced apart from each other, and having a wiring structure that connects the first and second surfaces to each other; a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure; a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers; a second passive component disposed in the second through-hole and connected to the redistribution layers; a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component; and a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip.

公开(公告)号：US10483197B2

公开(公告)日：2019-11-19

申请号：US15962867

申请日：2018-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Jung Jo ,  Hyung Joon Kim ,  Han Kim ,  Bo Min Jeong

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first connection member having a first surface and a second surface and including an insulating member and a first redistribution layer, a semiconductor chip connection electrodes disposed on the first connection member, an encapsulant on the second surface of the first connection member, including a photosensitive insulating material, and having a first region covering the active surface of the semiconductor chip and a second region in the vicinity of the semiconductor chip, a second redistribution layer including connection vias penetrating through the first region of the encapsulant, through-vias penetrating through the second region of the encapsulant, and a wiring pattern on the encapsulant and having an integrated structure with the connection vias and the through-vias, and a second connection member on the encapsulant including a third redistribution layer connected to the second redistribution layer.

公开(公告)号：USD832209S1

公开(公告)日：2018-10-30

申请号：US29613151

申请日：2017-08-08

Applicant: Samsung Electronics Co., Ltd.

Designer： Nam-Hyun Kang ,  Han Kim ,  Han-Kyung Ji

公开(公告)号：USD1043649S1

公开(公告)日：2024-09-24

申请号：US29884370

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Designer： Han Kim

Abstract: FIG. 1 is a front perspective view of a case for electronic device showing my new design;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is a rear perspective view thereof.
The broken lines in the figures illustrate portions of the case for electronic device that form no part of the claimed design.

公开(公告)号：USD1031713S1

公开(公告)日：2024-06-18

申请号：US29884355

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Designer： Han Kim

Abstract: FIG. 1 is a front perspective view of a case for electronic device showing my new design;
FIG. 2 is a front elevation view thereof;
FIG. 3 is a rear elevation view thereof;
FIG. 4 is a left side elevation view thereof;
FIG. 5 is a right side elevation view thereof;
FIG. 6 is a top plan view thereof;
FIG. 7 is a bottom plan view thereof; and,
FIG. 8 is a rear perspective view thereof.
The broken lines in the figures illustrate portions of the case for electronic device that form no part of the claimed design.