公开(公告)号：US10360034B2

公开(公告)日：2019-07-23

申请号：US15633746

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： David C. Tannenbaum ,  Srinivasan S. Iyer ,  Mitchell K. Alsup

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.