公开(公告)号：US11610785B2

公开(公告)日：2023-03-21

申请号：US17331751

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L21/60 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US20220130685A1

公开(公告)日：2022-04-28

申请号：US17331751

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun Lee ,  Kyoung Lim Suk ,  Ae-Nee Jang ,  Jaegwon Jang

IPC: H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.

公开(公告)号：US09024448B2

公开(公告)日：2015-05-05

申请号：US13785675

申请日：2013-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Gwon Jang ,  Young-Lyong Kim ,  Ae-Nee Jang

IPC: H01L23/48 ,  H01L23/495 ,  H01L21/56 ,  H01L23/13

CPC classification number: H01L23/49541 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L2224/16

Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.

Abstract translation: 半导体封装可以包括具有通孔的电路板芯片，安装在电路板芯片上的半导体器件和密封剂。 密封剂封装半导体器件，填充通孔并具有作为其中形成密封剂的模具的互补体的外部图案。 包装的一侧上的外部图案反映了模制形状，该模具形状相对于包装材料的相对侧上的密封剂材料流延迟封装材料的流动。