Abstract:
A liquid crystal display apparatus is provided which includes a pixel including a storage capacitor, wherein the storage capacitor is connected to be between a pixel electrode and a storage voltage line, a light sensing unit connected to be between the storage voltage line and a first node, and a transfer unit connected to transfer a voltage from the first node to a sensing line.
Abstract:
Provided is a display device. The display apparatus includes a plurality of data lines, a data driver, a plurality of gate lines, gate drivers, wherein the gate drivers includes first gate drivers connected to one end of a first group of the plurality of gate lines and second drivers connected to the other end of a second group of the plurality of gate lines, compensation circuits for compensating a rising time and falling time of gate signals outputted from the gate drivers, wherein the compensation circuits includes first compensation circuits connected to the other end of the first group of the plurality of gate lines and second compensation circuits connected to one end of the second group of the plurality of gate lines; and a plurality of pixels are respectively disposed on areas between the gate drivers.
Abstract:
A display device includes: a substrate partitioned into a display area including a plurality of pixels for displaying images thereon and a non-display area around the display area; a plurality of first gate lines and a plurality of data lines extended in one direction on the display area; a plurality of pads on one side of the non-display area; a plurality of gate fan-out lines, each coupling one of the first gate lines and a corresponding one of the pads; and a plurality of data fan-out lines, each coupling one of the data lines and a corresponding one of the pads, wherein the gate fan-out lines and the data fan-out lines may be alternately disposed.
Abstract:
There are provided a display device capable of detecting a defect of a scan driver. The display device includes pixels positioned in regions demarcated by scan lines and data lines, a scan driver including a plurality of stages connected to the scan lines, an inspection unit connected to the stages to detect whether the stages are defective, and including first transistors turned on when a control signal is supplied, and a timing controller supplying the control signal, wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.
Abstract:
An organic light-emitting diode display is disclosed. In one aspect, the display includes a plurality of data lines formed in a display area and a plurality of data pad portions formed in a non-display area and including a plurality of data pads and a plurality of dummy pads formed outside of the data pads. The display also includes a plurality of data fan-out portions electrically connected to the data pads and the data lines, and including a plurality of diagonal portions diagonally formed with respect to the data lines. The display also includes a plurality of voltage applying lines electrically connected to the dummy pads and insulated from the data fan-out portions, wherein at least one of the voltage applying lines intersects one or more of the diagonal portions.
Abstract:
A display panel includes a gate line extending in a column direction, a data line extending in a row direction, a pixel including a switching transistor connected to the gate line and the data line, and a voltage applier connected to a gate line of a present stage. The voltage applier to apply a voltage after conversion of the gate-on voltage to a gate-off voltage has started. The voltage is closer to the gate-on voltage than the gate-off voltage.
Abstract:
A display device includes: a gate electrode, a gate line, and data lines on a substrate, the data lines in a same layer as the gate line; a gate insulating layer on the gate line; a semiconductor member on the gate insulating layer; an etch stopper layer on the semiconductor member and the gate insulating layer; a first passivation layer on the etch stopper layer; a source electrode on the first passivation layer and the etch stopper layer and connected to the data lines; a drain electrode on the etch stopper layer; a common electrode on the first passivation layer and separated from the source electrode and the drain electrode; a second passivation layer on the source electrode, the drain electrode and the common electrode; and a pixel electrode on the second passivation layer and connected to the drain electrode.
Abstract:
An organic light-emitting diode display is disclosed. In one aspect, the display includes a plurality of data lines formed in a display area and a plurality of data pad portions formed in a non-display area and including a plurality of data pads and a plurality of dummy pads formed outside of the data pads. The display also includes a plurality of data fan-out portions electrically connected to the data pads and the data lines, and including a plurality of diagonal portions diagonally formed with respect to the data lines. The display also includes a plurality of voltage applying lines electrically connected to the dummy pads and insulated from the data fan-out portions, wherein at least one of the voltage applying lines intersects one or more of the diagonal portions.
Abstract:
A display device includes: a substrate partitioned into a display area including a plurality of pixels for displaying images thereon and a non-display area around the display area; a plurality of first gate lines and a plurality of data lines extended in one direction on the display area; a plurality of pads on one side of the non-display area; a plurality of gate fan-out lines, each coupling one of the first gate lines and a corresponding one of the pads; and a plurality of data fan-out lines, each coupling one of the data lines and a corresponding one of the pads, wherein the gate fan-out lines and the data fan-out lines may be alternately disposed.
Abstract:
A thin film transistor array panel including a first substrate, a gate conductor on the first substrate, a data conductor on the gate conductor, a shielding electrode on the data conductor and insulated from the data conductor, a passivation layer on the shielding electrode, and a pixel electrode on the passivation layer, in which the shielding electrode includes a vertical portion vertically extending along an edge of a pixel area and overlapped with the data line, and one or more horizontal portions connecting the vertical portions.