Abstract:
A thin film transistor “TFT”) substrate includes a substrate, an active layer over the substrate, and first and second TFTs over the substrate. The active layer includes: a first drain region, a first channel region and a first source region, which function as a drain, a channel and a source of the first TFT: a first lightly doped region between the first drain region and the first channel region: a second lightly doped region between the first channel region and the first source region: and a second drain region, a second channel region and a second source region, which function as a drain, a channel and a source of the second TFT. An impurity concentration at the second drain or source region is lower than an impurity concentration at the first drain or source region and higher than an impurity concentration at the first or second channel region.
Abstract:
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a thin film transistor (TFT) formed over the stretchable substrate and including a plurality of electrodes, an OLED electrically connected to the TFT and including a plurality of electrodes, and a plurality of interconnection lines connected to the electrodes of the OLED and the TFT. At least one of the interconnection lines is configured to move in a stretching direction and rotate an electrode selected from the electrodes of the OLED and the TFT connected to the at least one interconnection line.
Abstract:
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a thin film transistor (TFT) formed over the stretchable substrate and including a plurality of electrodes, an OLED electrically connected to the TFT and including a plurality of electrodes, and a plurality of interconnection lines connected to the electrodes of the OLED and the TFT. At least one of the interconnection lines is configured to move in a stretching direction and rotate an electrode selected from the electrodes of the OLED and the TFT connected to the at least one interconnection line.
Abstract:
A thin film transistor substrate and a display apparatus including the same are provided. The thin film transistor substrate includes a plurality of pixels each including: a first transistor for receiving a data signal in response to a first gate control signal; a second transistor for outputting a driving current according to the data signal applied to a gate electrode of the second transistor; and a third transistor for initializing a gate node connected to the gate electrode of the second transistor in response to a second gate control signal, wherein first electrodes of the third transistors of at least some adjacent pixels of the plurality of pixels are connected to the gate node, and second electrodes thereof are connected to a shared transistor that applies an initialization voltage to the second electrodes.
Abstract:
A display apparatus includes: a first display area comprising a first plurality of pixels; a second display area comprising transmission areas and a second plurality of pixels, wherein: the second plurality of pixels of the second display area are arranged in a buffer display area and a normal display area of the second display area; the buffer display area is adjacent to the first display area; the normal display area is spaced apart from the first display area; and a pixel density of the normal display area is less than a pixel density of the buffer display area; and a blocking metal layer in the second display area and comprising openings corresponding to the transmission areas.
Abstract:
A display apparatus includes: a pixel electrode; a pixel defining layer on the pixel electrode, and having an opening exposing at least a portion of the pixel electrode; a bank layer on the pixel defining layer; an overhang layer on the bank layer; an intermediate layer on the pixel electrode; and an opposite electrode on the intermediate layer. The overhang layer includes a tip protruding toward the pixel electrode from a point where a bottom surface of the overhang layer and a side surface of the bank layer facing toward the pixel electrode meet each other, and a height from an upper surface of the pixel defining layer to an upper surface of the bank layer is different from a height from the upper surface of the pixel defining layer to a bottom surface of the tip of the overhang layer.
Abstract:
An electronic device includes a display panel including pixels respectively connected to scan lines, scan stages corresponding to the scan lines, where each of the scan stages receives a carry signal, and outputs a scan signal, masking circuits electrically connected to some of the scan stages, respectively, where each of the masking circuits outputs a masking carry signal in response to a masking signal and the scan signal, and transmission circuits electrically connected to others of the scan stages, respectively, where each of the transmission circuits outputs the scan signal output from a corresponding scan stage among the scan stages. A j-th (j is an integer greater than 1) scan stage among the scan stages receives one of the scan signal output from a (j−1)-th scan stage and the masking carry signal as the carry signal.
Abstract:
A gate driver includes at least one stage, which includes: a first output circuit configured to supply a voltage of a first power source or a voltage of a second power source to a first output terminal and including a fourth capacitor connected between a second node and the first output terminal; a second output circuit configured to supply a signal supplied to a fourth input terminal or the voltage of the second power source to a second output terminal; an input circuit configured to control a voltage of the second node and a voltage of a third node; a first signal processor configured to control a voltage of a first node; a second signal processor configured to control the voltage of the second node; and a third signal processor connected between the first node and the third node, and configured to control the voltage of the first node.
Abstract:
A display device with a reduced area of dead spaces and a low defect occurrence rate includes a substrate including a display area and a peripheral area; and a first insulating layer disposed over the peripheral area and including a first side surface portion, a second side surface portion, and at least one recess portion. The first side surface portion includes a side surface aligned with a side surface of the substrate, and the second side surface portion includes a side surface aligned with the side surface of the substrate and is spaced apart from the first side surface portion. A first pad is disposed on the first insulating layer, extends to an edge of the substrate, fills the at least one recess portion, and includes a front end surface aligned with the side surface of the substrate.
Abstract:
A display panel includes a first display area having a first light transmittance and a second display area having a second light transmittance that is higher than the first light transmittance. The display panel further comprises a plurality of first pixels disposed in the first display area and a plurality of second pixels disposed in the second display area. A first power line is connected to the plurality of first pixels. The first power line is configured to provide a first power voltage. A second power line is connected to the plurality of second pixels. The second power line is configured to provide a second power voltage having a voltage level that is different from a voltage level of the first power voltage.