公开(公告)号：US20230282164A1

公开(公告)日：2023-09-07

申请号：US17961098

申请日：2022-10-06

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2330/021 ,  G09G2310/08 ,  G09G2320/0257

Abstract: A pixel includes a first switching transistor, a second switching transistor, a driving transistor, and a light emitting element. The first switching transistor includes a first terminal to which a bias power supply voltage is applied, a second terminal connected to a first node, and a gate terminal to which a light emitting element initialization signal is applied. The second switching transistor includes a first terminal connected to the first node, a second terminal connected to a second node, and a gate terminal to which the light emitting element initialization signal is applied. The driving transistor includes a first terminal connected to the second node, a second terminal connected to a third node, and a gate terminal. The light emitting element is connected to the driving transistor. The first node is connected to the third node, and the bias power supply voltage is applied to the second and third nodes.

公开(公告)号：US20220351673A1

公开(公告)日：2022-11-03

申请号：US17669887

申请日：2022-02-11

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: G09G3/32

Abstract: A panel repairing method includes detecting a defective portion of a panel, providing primary ink, which is ejected from an ink ejection pin, onto a first portion of the defective portion, spreading the primary ink in a direction parallel to a plane defined on the panel, temporarily curing the primary ink, providing secondary ink, which is ejected from the ink ejection pin, onto a second portion of the defective portion disposed adjacent to the first portion, and curing the primary ink and the secondary ink.

公开(公告)号：US20210391401A1

公开(公告)日：2021-12-16

申请号：US17244013

申请日：2021-04-29

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM ,  DOO-NA KIM ,  MEEJAE KANG ,  THANH TIEN NGUYEN

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3258

Abstract: A display device includes a pixel including a pixel driving transistor and a pixel switching transistor, the pixel driving transistor including a first active layer including a first channel area having a first length, a first gate insulating layer on the first active layer, a first gate electrode on the first gate insulating layer, a first source electrode and a first drain electrode above the first gate electrode, the pixel switching transistor including a second active layer including a second channel area having a second length that is shorter than the first length, a second gate insulating layer on the second active layer, a second gate electrode on the second gate insulating layer, a second source and a second drain electrode above the second gate electrode, and wherein the pixel driving transistor and the pixel switching transistor each include a P-MOS transistor.

公开(公告)号：US20240079420A1

公开(公告)日：2024-03-07

申请号：US18226986

申请日：2023-07-27

Applicant: Samsung Display Co., LTD.

Inventor： KEUNWOO KIM ,  TAEWOOK KANG ,  DOO-NA KIM ,  HANBIT KIM ,  JIYEONG SHIN ,  JUN HYUNG LIM

IPC: H01L27/12 ,  G09G3/3233 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1296 ,  G09G3/3233 ,  H01L27/1222 ,  H01L27/1237 ,  H01L29/408 ,  H01L29/66757 ,  H01L29/78675 ,  G09G2300/0819 ,  G09G2300/0842

Abstract: A display device includes a transistor including an active layer including first and second active areas, where the first active area includes a first drain area, a source area, and a first channel area between the source area and the first drain area, and the second active area includes the source area, a second drain area, and a second channel area between the source area and the second drain area, a gate insulating layer on the active layer, first and second charge layers at an interface between the first channel area and the gate insulating layer and at an interface between the second channel area and the gate insulating layer, where the first charge layer is adjacent to the source area, and the second charge layer is adjacent to the first and second drain areas and has a charge opposite to a charge of a first charge layer.

公开(公告)号：US20230422554A1

公开(公告)日：2023-12-28

申请号：US18104556

申请日：2023-02-01

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: H10K59/121

CPC classification number: H10K59/1213 ,  H10K59/1216

Abstract: A pixel circuit includes a first transistor a first gate terminal electrically connected to a gate node, a first terminal including polycrystalline silicon doped with a first impurity and electrically connected to a first voltage and a second terminal including polycrystalline silicon doped with the first impurity, and a second transistor a second gate terminal electrically connected to a first gate signal, a third terminal including polycrystalline silicon doped with a second impurity and electrically connected to the gate node and a fourth terminal including polycrystalline silicon doped with the second impurity.

公开(公告)号：US20230403880A1

公开(公告)日：2023-12-14

申请号：US18303327

申请日：2023-04-19

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: H10K59/121 ,  H10K59/131 ,  H10K59/12 ,  H10K71/20

CPC classification number: H10K59/1213 ,  H10K59/1216 ,  H10K59/131 ,  H10K59/1201 ,  H10K71/233

Abstract: A display apparatus including a pixel. The pixel includes a capacitor connected to a first voltage line, a light emitting element connected to a second voltage line, a first transistor including a first gate electrode connected to the capacitor, a second transistor connected to a data line and including a second gate electrode connected to the first scan line, a third transistor including a third gate electrode connected to a second scan line, and a fourth transistor including a fourth gate electrode connected to a third scan line, wherein at least one of the third transistor or the fourth transistor includes a plurality of active areas spaced apart from each other with a common conductive area therebetween, wherein at least one of the third gate electrode or the fourth gate electrode overlaps each of the common conductive area and the plurality of active areas in a plan view.

公开(公告)号：US20230245616A1

公开(公告)日：2023-08-03

申请号：US17982931

申请日：2022-11-08

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0842 ,  G09G2320/0247

Abstract: A pixel circuit includes a light emitting element, a driving transistor which applies a driving current to the light emitting element, a write transistor which receives a write gate signal and a data voltage and is connected to a first electrode of the driving transistor, a first compensation transistor which receives a compensation gate signal and is connected to a second electrode of the driving transistor and a first electrode of a second compensation transistor, the second compensation transistor which receives the compensation gate signal, and is connected to the second electrode of the first compensation transistor and a control electrode of the driving transistor, a storage capacitor which receives a first power voltage and is connected to the control electrode of the driving transistor, and a node control transistor which receives the write gate signal and is connected to the second electrode of the first compensation transistor.

公开(公告)号：US20230026562A1

公开(公告)日：2023-01-26

申请号：US17739501

申请日：2022-05-09

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM ,  TAEWOOK KANG ,  JANG-HYUN KIM ,  JOON WOO BAE ,  JAESEOB LEE ,  DONGGYU JIN ,  SANGGUN CHOI

IPC: H01L27/32

Abstract: A display device includes a first transistor, a second transistor electrically connected thereto, n third transistors electrically connected to a gate of the first transistor and connected to each other in series, a capacitor to be charged with a voltage corresponding to a data signal, and a light emitting element, wherein the third transistors include a semiconductor area including a channel area, a source area, a drain area, and a gate overlapping the channel area, wherein the source area or the drain area that is closer to the gate of the first transistor, and that is of the third transistor closest to the gate of the first transistor, includes a first area, and a second area between the first area and the channel area, having a doping concentration that is lower than that of the first area, and having a width that is less than that of the first area.

公开(公告)号：US20220415255A1

公开(公告)日：2022-12-29

申请号：US17684227

申请日：2022-03-01

Applicant: Samsung Display Co., Ltd.

Inventor： HANBIT KIM ,  MEEJAE KANG ,  KEUNWOO KIM ,  DOO-NA KIM ,  SANGSUB KIM ,  DOKYEONG LEE ,  JAEHWAN CHU

IPC: G09G3/3233

Abstract: A pixel includes a first capacitor connected between a first electrode and a second electrode connected to a first node, a first transistor including a gate electrode connected to the first node, a first electrode connected to a second node, and a second electrode connected to a third node, a second transistor including a gate electrode that receives a data write gate signal, a first electrode that receives a data voltage, and a second electrode connected to the second node, a third transistor connected between the first node and the third node, a fourth transistor connected between the first node and an initialization voltage input terminal to which an initialization voltage is applied, an eighth transistor t connected to the third transistor and the fourth transistor, and an organic light emitting diode including an anode and a cathode receiving a second power supply voltage.

公开(公告)号：US20220285404A1

公开(公告)日：2022-09-08

申请号：US17455188

申请日：2021-11-16

Applicant: Samsung Display Co., Ltd.

Inventor： KEUNWOO KIM

IPC: H01L27/12

Abstract: A display device includes a substrate including a polymer film, a first active pattern above the substrate, and including a first channel region, a gate electrode above the first active pattern, and overlapping the first channel region, a first storage capacitor electrode above the gate electrode, and overlapping the gate electrode, a second active pattern at a layer above the first storage capacitor electrode, and including a second channel region, a first gate line above the second active pattern, and overlapping the second channel region, and a blocking pattern between the first channel region and the first gate line in a plan view.