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公开(公告)号：US20210343822A1
公开(公告)日：2021-11-04
申请号：US17223505
申请日：2021-04-06
Applicant: Samsung Display Co., LTD.
Inventor： Kyungjin JEON , Soyoung KOO , Eok Su KIM , Hyungjun KIM , Yunyong NAM , Jun Hyung LIM
IPC: H01L27/32
Abstract: An electronic apparatus includes a first transistor including a first oxide semiconductor pattern, a second transistor including a second oxide semiconductor pattern, a blocking layer including a conductive material, a signal line including a first line and a second line which are disposed on different layers, and a bridge pattern electrically connected to each of the first transistor, the first line of the signal line, and the second line of the signal line, wherein the first line of the signal line and the blocking layer are disposed on a same layer, and the second line of the signal line and the first oxide semiconductor pattern are disposed on a same layer.
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公开(公告)号：US20210249499A1
公开(公告)日：2021-08-12
申请号：US17074323
申请日：2020-10-19
Applicant: Samsung Display Co., Ltd.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Jun Hyung LIM
IPC: H01L27/32
Abstract: A display device and a method of driving a display device are provided. A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern, a buffer layer on the first conductive layer, a semiconductor layer including a semiconductor pattern on the buffer layer, a gate insulating layer on the semiconductor pattern, a second conductive layer including a gate electrode on the gate insulating layer, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including a first conductive pattern electrically coupling the lower light blocking pattern to the semiconductor pattern, wherein the first conductive pattern is coupled to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor pattern through a second contact hole passing through the planarization layer.
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公开(公告)号：US20180175076A1
公开(公告)日：2018-06-21
申请号：US15842424
申请日：2017-12-14
Applicant: Samsung Display Co., Ltd.
Inventor： Eok Su KIM , Jay Bum KIM , Kyoung Seok SON , Jun Hyung LIM
IPC: H01L27/12 , H01L29/786
Abstract: A transistor array panel according to an exemplary embodiment includes: a substrate; a first buffer layer positioned on the substrate; and a first transistor and a second transistor positioned on the substrate and separated from each other, wherein the first transistor includes a polycrystalline semiconductor positioned on the substrate, and a first gate electrode overlapping the polycrystalline semiconductor, the second transistor includes an oxide semiconductor positioned on the first buffer layer, and a second gate electrode overlapping the oxide semiconductor, the first buffer layer covers the first gate electrode, and the first buffer layer includes a silicon oxide.
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公开(公告)号：US20240128251A1
公开(公告)日：2024-04-18
申请号：US18395966
申请日：2023-12-26
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Yun Yong NAM , Jun Hyung LIM
CPC classification number: H01L25/167 , H01L27/124 , H01L27/1259
Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
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公开(公告)号：US20240121983A1
公开(公告)日：2024-04-11
申请号：US18368461
申请日：2023-09-14
Applicant: Samsung Display Co., LTD.
Inventor： So Young KOO , Myoung Hwa KIM , Eok Su KIM , Hyung Jun Kim
IPC: H10K59/121 , H10K59/12 , H10K59/126 , H10K59/131
CPC classification number: H10K59/1213 , H10K59/1201 , H10K59/1216 , H10K59/126 , H10K59/131
Abstract: A thin film transistor includes a substrate; an active layer including a channel area, a first conductive area, and a second conductive area; a gate insulating layer on a portion of the active layer; a first through hole penetrating through a portion of the first conductive area; a second through hole penetrating through a portion of the second conductive area; a gate electrode overlapping the channel area of the active layer; a first electrode electrically connected to the first conductive area; and a second electrode electrically connected to the second conductive area. One side of the first electrode adjacent to the first through hole is parallel to the one side of the first through hole, the first electrode including protrusion parts at both ends thereof and a groove part concavely recessed from the gate electrode.
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Patent Agency Ranking
公开(公告)号：US20240040870A1
公开(公告)日：2024-02-01
申请号：US18230281
申请日：2023-08-04
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Jun Hyung LIM
IPC: H10K59/131 , H10K59/122
CPC classification number: H10K59/131 , H10K59/122 , H10K59/1201
Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.
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公开(公告)号：US20230253415A1
公开(公告)日：2023-08-10
申请号：US18193200
申请日：2023-03-30
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Joon Seok PARK , Jun Hyung LIM
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1262 , H10K59/131
Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.
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公开(公告)号：US20230189585A1
公开(公告)日：2023-06-15
申请号：US17943133
申请日：2022-09-12
Applicant: Samsung Display Co., Ltd.
Inventor： Yun Yong NAM , So Young KOO , Eok Su KIM , Hyung Jun KIM , Jun Hyung LIM , Kyung Jin JEON
CPC classification number: H01L27/3276 , H01L51/56 , H01L51/5253 , H01L51/524 , H01L27/3246 , H01L27/3272
Abstract: The present disclosure relates to a display panel and a method for fabricating the same. According to an embodiment, a method for fabricating a display panel, comprises disposing a circuit array and connection lines on the support substrate, the circuit array disposed in the display area, the connection lines disposed in a non-display area; disposing a via layer on the support substrate; providing a sealing hole surrounding the display area by patterning the via layer; disposing a sealing member surrounding the display area on an encapsulation substrate. In the disposing of the circuit array and the connection lines comprises disposing an active layer overlapping a light shielding member and disposing an etch stopper corresponding to at least a portion of an overlapping area between the sealing hole and the first connecting line part, by patterning a semiconductor material layer on the buffer layer.
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公开(公告)号：US20220165759A1
公开(公告)日：2022-05-26
申请号：US17469217
申请日：2021-09-08
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Yun Yong NAM , Jun Hyung LIM
Abstract: A display device and a method of manufacturing a display device are provided. The display device includes a first conductive layer on a substrate, a passivation layer disposed on the first conductive layer and exposing at least a part of the first conductive layer, a second conductive layer disposed on the passivation layer and covering an upper surface of the passivation layer, a via layer on the second conductive layer, a third conductive layer including a first electrode, a second electrode, and a connection pattern, and spaced apart from each other on the via layer, and a light emitting element having ends that are disposed on the first electrode and the second electrode, respectively. The connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer.
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公开(公告)号：US20220115364A1
公开(公告)日：2022-04-14
申请号：US17471581
申请日：2021-09-10
Applicant: Samsung Display Co., LTD.
Inventor： Kyung Jin JEON , So Young KOO , Eok Su KIM , Hyung Jun KIM , Yun Yong NAM , Jun Hyung LIM
Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
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