公开(公告)号：US10431547B2

公开(公告)日：2019-10-01

申请号：US15870910

申请日：2018-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geol Nam ,  Young Lyong Kim

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.

公开(公告)号：US20250087603A1

公开(公告)日：2025-03-13

申请号：US18616875

申请日：2024-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyun Soo Chung

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A semiconductor package includes an interposer structure extending in a first direction and including an inner area and an outer area defined by an inner area, a first semiconductor chip mounted on the inner area and electrically connected to the interposer structure, a plurality of bumps disposed between the first semiconductor chip and the interposer structure, and contacting each of the first semiconductor chip and the interposer structure, an underfill filling a space between the interposer structure and the first semiconductor chip and covering the plurality of bumps; and a mold layer disposed on the outer area and surrounding the first semiconductor chip, wherein the interposer structure includes a decoupling capacitor, wherein a ratio of a length in the first direction of the first semiconductor chip to a length in the first direction of the interposer structure is in a range of 0.9 inclusive to 1 exclusive.

公开(公告)号：US12100635B2

公开(公告)日：2024-09-24

申请号：US17185116

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Jung ,  Young Lyong Kim ,  Cheolsoo Han

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L25/18 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/92 ,  H01L2224/32054 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83939 ,  H01L2224/92125

Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.

公开(公告)号：US11705430B2

公开(公告)日：2023-07-18

申请号：US17183786

申请日：2021-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeong Kim ,  Young Lyong Kim ,  Geol Nam

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/17 ,  H01L21/561 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

公开(公告)号：US10770446B2

公开(公告)日：2020-09-08

申请号：US16201021

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Lyong Kim ,  Jin-woo Park ,  Choongbin Yim ,  Younji Min

IPC: H01L23/58 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L25/10 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.