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公开(公告)号：US20220029095A1
公开(公告)日：2022-01-27
申请号：US17192093
申请日：2021-03-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Hyeoungwon SEO , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A vertical variable resistance memory device including gate electrodes spaced apart from each other in a first direction on a substrate, each of the gate electrodes including graphene and extending in a second direction, the first direction being substantially perpendicular to an upper surface of the substrate and the second direction being substantially parallel to the upper surface of the substrate; first insulation patterns between the gate electrodes, each of the first insulation patterns including boron nitride (BN); and at least one pillar structure extending in the first direction through the gate electrodes and the first insulation patterns on the substrate, wherein the at least one pillar structure includes a vertical gate electrode extending in the first direction; and a variable resistance pattern on a sidewall of the vertical gate electrode.
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公开(公告)号：US20200280868A1
公开(公告)日：2020-09-03
申请号：US16878065
申请日：2020-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyunseok RYU , Yongseok KIM , Peng XUE , Hyunkyu YU , Sangwon CHOI , Kuyeon WHANG
Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided, which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.
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公开(公告)号：US20190228203A1
公开(公告)日：2019-07-25
申请号：US16253533
申请日：2019-01-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghoo KIM , Suna KIM , Valeriy PRUSHINSKIY , Suk HYUN , Yongseok KIM , Changryong HEO
Abstract: A fingerprint sensor and an electronic device are provided. The fingerprint sensor includes a refractive member configured to refract light into a path toward at least one optical sensor, wherein the at least one optical sensor is configured to obtain the light, and a guide member disposed between the refractive member and the at least one optical sensor and configured to provide the path so that the refracted light is transmitted to the at least one optical sensor. The electronic device includes transparent cover; light source configured to output light toward transparent cover; refractive member configured to refract light into path toward at least one optical sensor; wherein at least one optical sensor is configured to obtain light; and guide member disposed between refractive member and at least one optical sensor and configured to provide path so that refracted light is transmitted to at least one optical sensor.
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公开(公告)号：US20180138960A1
公开(公告)日：2018-05-17
申请号：US15806132
申请日：2017-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seokki AHN , Kwangtaik KIM , Yongseok KIM , Chiwoo LIM
Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.According to various embodiments of the present disclosure, a CQI transmission method of a terminal in a wireless communication system includes: estimating a channel of a serving base station and an interference base station to which sliding-window superposition coding (SWSC) is applied; generating channel quality information (CQI)-related information on the serving base station and the interference base station based on the estimated channel to indicate an achievable rate region; and transmitting the generated CQI-related information. However, the present disclosure is not limited to the above embodiment, and therefore other embodiments are possible.
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公开(公告)号：US20250113590A1
公开(公告)日：2025-04-03
申请号：US18976522
申请日：2024-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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Patent Agency Ranking
公开(公告)号：US20240276733A1
公开(公告)日：2024-08-15
申请号：US18405361
申请日：2024-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Sanghyun PARK , Kiheun LEE , Sangwoo HAN
Abstract: A semiconductor memory device includes a substrate, a semiconductor pattern on the substrate and including a source region having a first conductivity type, a drain region having a second conductivity type, and an intrinsic region between the source region and the drain region, first and second gate electrodes on the intrinsic region, a ferroelectric pattern between the intrinsic region and the first and second gate electrodes, and a gate dielectric pattern between the ferroelectric pattern and the intrinsic region.
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公开(公告)号：US20230307551A1
公开(公告)日：2023-09-28
申请号：US18092973
申请日：2023-01-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungwon YOO , Yongseok KIM , Min Tae RYU , Huije RYU , Yongjin LEE , Wonsok LEE , Min Hee CHO
IPC: H01L29/786 , H10B12/00 , H01L27/146 , H01L29/417
CPC classification number: H01L29/78693 , H01L27/10814 , H01L27/14616 , H01L29/41733 , H01L29/78696
Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.
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公开(公告)号：US20230180453A1
公开(公告)日：2023-06-08
申请号：US18054986
申请日：2022-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Kyunghwan LEE , Minjun LEE , Daewon HA
IPC: H01L27/108
CPC classification number: H01L27/10802
Abstract: A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.
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公开(公告)号：US20230101700A1
公开(公告)日：2023-03-30
申请号：US17881747
申请日：2022-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC: H01L27/108
Abstract: A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.
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公开(公告)号：US20210225842A1
公开(公告)日：2021-07-22
申请号：US16999378
申请日：2020-08-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC: H01L27/102 , H01L29/24
Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.
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