公开(公告)号：US09614529B1

公开(公告)日：2017-04-04

申请号：US15012696

申请日：2016-02-01

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/00 ,  H03K19/0185

CPC classification number: H03K19/018507 ,  H03K19/0016 ,  H03K19/018514

Abstract: An input/output (I/O) driver that includes circuitry for over-voltage protection of first and second FETs coupled in series between a first rail and an output, and third and fourth FETs coupled between the output and a second rail. The circuitry is configured to generate a gate bias voltage for the second FET that transitions from high to low bias voltages state when the output voltage (VPAD) begins transitioning from low to high logic voltages, and transitions back to the high bias voltage while VPAD continues to transition towards the high logic voltage. Further, the circuitry is configured to generate a gate bias voltage for the third FET that transitions from low to high bias voltages when VPAD begins transitioning from high to low logic voltages, and transitions back to the low bias voltage while VPAD continues to transition towards the low logic voltage.

公开(公告)号：US09202535B2

公开(公告)日：2015-12-01

申请号：US13797775

申请日：2013-03-12

Applicant: QUALCOMM Incorporated

Inventor： Chang Ki Kwon ,  Wilson Jianbo Chen ,  Reza Jalilizeinali

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/1084

Abstract: In a particular embodiment, a method includes modifying an output impedance associated with the input receiver. In response to modifying the output impedance, the method restricts an output voltage at an output node of the input receiver. Particular embodiments of an input receiver circuit are also disclosed.

Abstract translation: 在特定实施例中，一种方法包括修改与输入接收器相关联的输出阻抗。 响应于修改输出阻抗，该方法限制输入接收器的输出节点处的输出电压。 还公开了输入接收机电路的特定实施例。

公开(公告)号：US20150303906A1

公开(公告)日：2015-10-22

申请号：US14254706

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：US08754677B2

公开(公告)日：2014-06-17

申请号：US13683053

申请日：2012-11-21

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/00

CPC classification number: G05F1/565

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract translation: 公开了一种输入/输出（I / O）驱动器，其采用补偿电路来限制驱动器的器件之间的电压超过限定的阈值，以允许较低电压的器件实现驱动器的操作。 特别地，驱动器采用包括耦合在第一电压轨和驱动器的输出之间的第一和第二开关器件的上拉电路。 驱动器采用包括耦合在输出端和第二电压轨道之间的第三和第四开关器件的下拉电路。 I / O驱动器采用补偿电路，其被配置为在适当的时间向第一和第二开关器件之间的节点和第三和第四开关器件之间的节点施加补偿电压，以保持跨越第二和第三开关器件的相应电压 在驾驶员的操作期间，切换设备处于或低于定义的阈值，例如可靠性限制。