公开(公告)号：US09195466B2

公开(公告)日：2015-11-24

申请号：US13676146

申请日：2012-11-14

Applicant: QUALCOMM Incorporated

Inventor： Melinda J. Brown ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Andrew S. Irwin ,  Michael William Morrow

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

Abstract: Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

Abstract translation: 公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。 在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。 该电路还基于评估与第一条件逻辑相反的第二条件，检测向目标寄存器写入第二值的第二条件写入指令。 选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。 如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

公开(公告)号：US10108419B2

公开(公告)日：2018-10-23

申请号：US14498938

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Melinda Joyce Brown

IPC: G06F9/40 ,  G06F9/42 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38

Abstract: Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.

公开(公告)号：US20140281394A1

公开(公告)日：2014-09-18

申请号：US13833844

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Rodney Wayne Smith ,  Jeffery M. Schottmiller ,  Michael Scott McIlvaine ,  Brian Michael Stempel ,  Melinda J. Brown ,  Daren Eugene Streett

IPC: G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/30054 ,  G06F9/3806

Abstract: An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.

Abstract translation: 一种用于通过利用链路寄存器堆栈在处理器中执行呼叫分支和返回分支指令的装置和方法。 处理器包括初始化为零的分支计数器，并且每当处理器解码除了呼叫分支指令之外的链接寄存器操作指令时，该分支计数器被设置为零。 每当一个呼叫转移指令被解码并且一个地址被推到链路寄存器堆栈上时，分支计数器递增1。 响应于解码返回分支指令并且提供的分支计数器不为零，解码的返回分支指令的目标地址从链接寄存器堆栈中弹出，分支计数器递减，并且不需要检查目标地址 为正确。