公开(公告)号：US20160294585A1

公开(公告)日：2016-10-06

申请号：US14852088

申请日：2015-09-11

Applicant: QUALCOMM Incorporated

Inventor： Mohammed Mizanur Rahman ,  Thomas Clark Bryan ,  Jacob Stephen Schneider ,  LuVerne Ray Peterson ,  Tin Tin Wee ,  Alvin Leng Sun Loke

IPC: H04L25/08 ,  H04B1/16

CPC classification number: H04L25/03885 ,  H04B1/16 ,  H04L25/0278 ,  H04L25/029 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03 ,  H04L25/03834 ,  H04L25/03878 ,  H04L25/08

Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but-for the equalizer.

Abstract translation: 公开了使用不匹配阻抗和均衡器来提供接收和捕获数据以节省功率的方法，系统和电路。 一种与传输线通信的数据接收机，所述数据接收机具有相对于所述传输线的特性阻抗失配的终端阻抗; 以及与数据接收器通信的均衡器，均衡器被配置为从数据接收器接收信道发送的数据信号并且重新形成信号以减小失真RC衰减; 其中所述电路被配置为以第一模式可选择地操作，其中终端阻抗相对于传输线的特性阻抗匹配，以及第二模式，其中终端阻抗相对于传输线的特性阻抗失配， 信号是不可恢复的，但是对于均衡器。

公开(公告)号：US20160019179A1

公开(公告)日：2016-01-21

申请号：US14335712

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Tin Tin Wee ,  Thomas Clark Bryan

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4072 ,  G06F13/4208

Abstract: Circuits and methods for Data Bus Inversion (DBI) are provided. In one example, the immediately previous value of the DBI bit affects the next value of the DBI bit. Specifically, in some instances, the value of the DBI bit is held to the immediately previous value of the DBI bit to limit the total number of transitions on a data bus.

Abstract translation: 提供了数据总线反转（DBI）的电路和方法。 在一个示例中，DBI位的紧接之前的值会影响DBI位的下一个值。 具体地说，在某些情况下，DBI位的值被保持到DBI位的紧前一个值，以限制数据总线上的转换总数。