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公开(公告)号：US10521321B2
公开(公告)日：2019-12-31
申请号：US15850967
申请日：2017-12-21
Applicant: QUALCOMM Incorporated
Inventor： Alex Kwang Ho Jong , Jay Chunsup Yun , Donghyun Kim , Rahul Gulati , Brendon Lewis Johnson , Andrew Evan Gruber
IPC: G06F11/00 , G06F11/277 , G06T1/20 , G06T7/00 , G06F11/22
Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.
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公开(公告)号：US10467723B2
公开(公告)日：2019-11-05
申请号：US15850907
申请日：2017-12-21
Applicant: QUALCOMM Incorporated
Inventor： Brendon Lewis Johnson , Andrew Evan Gruber , Jay Chunsup Yun , Rahul Gulati , Donghyun Kim , Alex Kwang Ho Jong
Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.
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公开(公告)号：US20150235341A1
公开(公告)日：2015-08-20
申请号：US14182976
申请日：2014-02-18
Applicant: QUALCOMM Incorporated
Inventor： Chunhui Mei , Vineet Goel , Donghyun Kim
CPC classification number: G06T1/60 , G06T1/20 , G06T15/005 , G06T15/80
Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.
Abstract translation: 图形处理单元（GPU）可以在图形处理流水线的至少两个阶段共享的GPU的片上图形存储器中分配共享数据信道。 GPU中的着色器单元可以执行图形处理流水线的至少两个阶段。 GPU可以在片上图形存储器的共享数据通道中存储在着色器单元上执行的图形处理流水线的至少两个阶段中的每一个生成的数据。
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公开(公告)号：US20130265308A1
公开(公告)日：2013-10-10
申请号：US13830075
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vineet Goel , Andrew E. Gruber , Donghyun Kim
IPC: G06T15/80
Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.
Abstract translation: 本公开的方面涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件单元执行顶点着色操作以遮蔽输入顶点以输出顶点着色顶点，其中， 硬件单元遵循接收单个顶点作为输入并生成单个顶点作为输出的接口。 该过程还包括使用指定用于顶点着色的GPU的硬件单元执行船体着色操作，以基于顶点着色顶点中的一个或多个生成一个或多个控制点，其中所述一个或多个船体着色操作操作 所述一个或多个顶点着色顶点中的至少一个以输出所述一个或多个控制点。
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