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    Integrating ramp circuit with reduced ramp settling time
    21.
    发明授权
    Integrating ramp circuit with reduced ramp settling time 有权

    公开(公告)号：US10826470B2

    公开(公告)日：2020-11-03

    申请号：US16352673

    申请日：2019-03-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Liang Zuo ,  Rui Wang ,  Hiroaki Ebihara ,  Nijun Jiang

    IPC: H03K4/56 ,  H04N5/3745 ,  H03M1/56 ,  H04N5/378 ,  H04N5/369 ,  H03F3/45

    Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

    CMOS image sensor with divided bit lines
    22.
    发明授权
    CMOS image sensor with divided bit lines 有权

    公开(公告)号：US10750111B2

    公开(公告)日：2020-08-18

    申请号：US16222832

    申请日：2018-12-17

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Rui Wang ,  Zheng Yang ,  Eiichi Funatsu

    IPC: H04N5/378 ,  H01L27/146 ,  H04N5/374

    Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line coupled to a column of pixels is separated in to a plurality of electrically portions that are coupled to corresponding portions of rows of the pixel array. A first switching circuit of a readout circuit is coupled to the bit line. A first switching circuit is configured to couple a bit line current source to the bit line to provide a DC current coupled to flow through the bit line and through the first switching circuit during a readout operation of a pixel coupled to the bit line. A second switching circuit is configured to couple and ADC to the bit line during the readout operation of the pixel. Substantially none of the DC current provided by the bit line current source flows through the second switching circuit during the readout operation of the pixel.

    SMALL PIXELS HAVING DUAL CONVERSION GAIN PROVIDING HIGH DYNAMIC RANGE
    23.
    发明申请
    SMALL PIXELS HAVING DUAL CONVERSION GAIN PROVIDING HIGH DYNAMIC RANGE 审中-公开

    公开(公告)号：US20190386057A1

    公开(公告)日：2019-12-19

    申请号：US16008434

    申请日：2018-06-14

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Zheng Yang ,  Hiroaki Ebihara ,  Tiejun Dai

    IPC: H01L27/146

    Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

    Low noise CMOS image sensor by stack architecture
    26.
    发明授权
    Low noise CMOS image sensor by stack architecture 有权

    公开(公告)号：US10218924B2

    公开(公告)日：2019-02-26

    申请号：US15485534

    申请日：2017-04-12

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Sohei Manabe ,  Keiji Mabuchi ,  Takayuki Goto ,  Duli Mao ,  Hiroaki Ebihara ,  Kazufumi Watanabe

    IPC: H04N5/335 ,  H01L27/146 ,  H04N5/374 ,  H04N5/378 ,  H04N5/355 ,  H04N5/3745

    Abstract: A pixel circuit for use in a high dynamic range (HDR) image sensor includes a photodiode and a floating diffusion is disposed in the first semiconductor wafer. A transfer transistor is disposed in the first semiconductor wafer and is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion. An in-pixel capacitor is disposed in a second semiconductor wafer. The first semiconductor wafer is stacked with and coupled to the second semiconductor wafer. A dual floating diffusion (DFD) transistor is disposed in the first semiconductor wafer. The in-pixel capacitor is selectively coupled to the floating diffusion through the DFD transistor. The floating diffusion is set to low conversion gain in response to the in-pixel capacitor being coupled to the floating diffusion, and high conversion gain in response to the in-pixel capacitor being decoupled from the floating diffusion.

    Method and system for implementing H-banding cancellation in an image sensor
    27.
    发明授权
    Method and system for implementing H-banding cancellation in an image sensor 有权

    公开(公告)号：US09838621B2

    公开(公告)日：2017-12-05

    申请号：US15147741

    申请日：2016-05-05

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Zheng Yang ,  Hiroaki Ebihara

    IPC: H04N5/341 ,  H04N5/374

    CPC classification number: H04N5/341 ,  H04N5/357 ,  H04N5/374 ,  H04N5/378

    Abstract: A method for implementing H-Banding cancellation in an image sensor starts with a pixel array capturing image data. Pixel array includes a plurality of pixels to generate pixel data signals, respectively. ADC circuitry acquires the pixel data signals. ADC circuitry includes a comparator circuitry. In one embodiment, comparator circuitry 310 includes a plurality of comparators. Comparators included in comparator circuitry compare the pixel data signals, respectively, to a ramp signal received from a ramp generator to generate comparator output signals. Adjacent comparators output signals may be opposite in polarity. Other embodiments are described.

    DISTRIBUTED RAMP LINEARITY COMPENSATION CIRCUIT
    28.
    发明申请
    DISTRIBUTED RAMP LINEARITY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20250048002A1

    公开(公告)日：2025-02-06

    申请号：US18363469

    申请日：2023-08-01

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Nobuhiro Yanagisawa ,  Satoshi Sakurai ,  Tomoyasu Tate ,  Naoki Kitazawa ,  Kohei Harada

    IPC: H04N25/78 ,  H04N25/709 ,  H04N25/76

    Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS
    29.
    发明申请
    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS 有权

    公开(公告)号：US20250047995A1

    公开(公告)日：2025-02-06

    申请号：US18363473

    申请日：2023-08-01

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liang Zuo ,  Hiroaki Ebihara ,  Jing Jun Yi ,  Rui Wang ,  Satoshi Sakurai

    IPC: H04N25/677 ,  H04N25/766 ,  H04N25/772

    Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

    DYNAMIC CURRENT CONTROL FOR COLUMN ADC
    30.
    发明公开
    DYNAMIC CURRENT CONTROL FOR COLUMN ADC 审中-公开

    公开(公告)号：US20240291499A1

    公开(公告)日：2024-08-29

    申请号：US18176373

    申请日：2023-02-28

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Chengcheng Xu ,  Satoshi Sakurai ,  Kenny Geng

    IPC: H03M1/46

    CPC classification number: H03M1/466 ,  H03M1/462

    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

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