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公开(公告)号：US11606155B2
公开(公告)日：2023-03-14
申请号：US17374108
申请日：2021-07-13
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jinhui Wang , Chuan Xu
Abstract: A method for exchanging a clock synchronization packet performed by a network apparatus, including: exchanging a clock synchronization packet with a first clock source, where the network apparatus includes a boundary clock; determining a first time deviation of the boundary clock relative to the first clock source according to the clock synchronization packet exchanged with the first clock source, where the boundary clock avoids performing an operation of calibrating a time of a local clock of the boundary clock according to the first time deviation; and sending a clock synchronization packet to a first slave clock of the boundary clock, where the clock synchronization packet includes a first timestamp, a value of the first timestamp is equal to a first corrected value, and the first corrected value is a value obtained by the boundary clock by correcting the time of the local clock by using the first time deviation.
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公开(公告)号：US20230034757A1
公开(公告)日：2023-02-02
申请号：US17965117
申请日：2022-10-13
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tongfu Wu , Tao He , Jingfei Lv , Hao Li , Jinhui Wang
Abstract: A method, a device, and a system, the method including determining, by a management device, a first transmission path that is in a network system and that is used to transmit a clock packet of a target clock source, sending, by the management device, configuration information for the first transmission path to a plurality of network devices on the first transmission path, receiving, by the management device, information that is sent by an endpoint network device on the first transmission path and that is used to determine a time difference, and sending, by the management device, a corresponding clock compensation value to at least one network device on the first transmission path based on the information that is used to determine the time difference.
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公开(公告)号：US20220140929A1
公开(公告)日：2022-05-05
申请号：US17576423
申请日：2022-01-14
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinhui Wang , Liqing Chen , Hongwei Niu , Yunlei Qi
IPC: H04J3/06
Abstract: A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and where the second packet is the first packet processed by the media conversion module, and calculating a time interval T1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.
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公开(公告)号：US11245483B2
公开(公告)日：2022-02-08
申请号：US16797225
申请日：2020-02-21
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinhui Wang , Liqing Chen , Hongwei Niu , Yunlei Qi
IPC: H04J3/06
Abstract: A packet processing method includes receiving a first packet by a first receiving interface of a media conversion module of a first network device, where the first packet includes a first alignment marker (AM), sending a second packet by a first sending interface of the media conversion module, where the second packet includes the first AM, and the second packet is the first packet processed by the media conversion module, and calculating a time interval T1 between a time at which the media conversion module receives the first packet and a time at which the media conversion module sends the second packet, where the T1 is used to compensate for a first timestamp at which the first network device receives or sends the third packet.
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Patent Agency Ranking
公开(公告)号：US20210409140A1
公开(公告)日：2021-12-30
申请号：US17471676
申请日：2021-09-10
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jingfei Lv , Boling Fan , Jinhui Wang , Liqing Chen
Abstract: A clock synchronization packet exchanging method includes sending, by a first device in a Flexible Ethernet (FlexE) group, a first FlexE instance at a first physical layer (PHY), where the first FlexE instance includes a clock synchronization packet, and a second FlexE instance sent by the first device in the FlexE group at a second PHY also includes a clock synchronization packet. The clock synchronization packets are carried in a plurality of FlexE instances transmitted between a transmit end and a receive end in the FlexE group.
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公开(公告)号：US11171769B2
公开(公告)日：2021-11-09
申请号：US16914453
申请日：2020-06-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xingjian Shi , Jinhui Wang , Chuan Xu
Abstract: In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.
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公开(公告)号：US20200328872A1
公开(公告)日：2020-10-15
申请号：US16914453
申请日：2020-06-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xingjian Shi , Jinhui Wang , Chuan Xu
Abstract: In various embodiments, a method is provided. In this method, a first signal is received from a master node, and is sampled to obtain a first sample. The first sample is then quantized to obtain a quantized form of the first sample. A first synchronization sequence is detected from the quantized form of the first sample at T2. First information is received from the master node and the first information is used to indicate a moment T1 at which the master node sends the first synchronization sequence. A second synchronization sequence is sent to the master node at T3. Second information received from the master node and the second information is used to indicate a moment T4 at which the master node detects a quantized form of the second synchronization sequence. Time synchronization is performed based on T1, T2, T3, and T4.
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公开(公告)号：US20190260490A1
公开(公告)日：2019-08-22
申请号：US16401996
申请日：2019-05-02
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jingfei Lv , Jinhui Wang , Chuan Xu
IPC: H04J3/06
Abstract: A frequency synchronization method includes: receiving, by a slave clock, a first pulse signal and a second pulse signal; determining, by the slave clock based on a first phase difference, a second phase difference, a first delay, and a second delay, that a frequency offset of the slave clock relative to the master clock is equal to a first frequency offset, where the first phase difference is a difference between a phase of a third pulse signal generated by the slave clock and a phase of the first pulse signal received by the slave clock, and the second phase difference is a difference between a phase of a fourth pulse signal generated by the slave clock and a phase of the second pulse signal received by the slave clock; and calibrating, by the slave clock, frequency of the slave clock based on the first frequency offset.
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公开(公告)号：US20190165927A1
公开(公告)日：2019-05-30
申请号：US16265617
申请日：2019-02-01
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jinhui Wang
CPC classification number: H04L7/0087 , H03L7/00 , H03L7/22 , H04J3/0685 , H04J3/0688 , H04J3/0691 , H04J3/0697 , H04L7/06
Abstract: A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.
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