-
公开(公告)号：US20110133804A1
公开(公告)日：2011-06-09
申请号：US12631661
申请日：2009-12-04
CPC分类号： H03K3/13 , H03K3/011 , H03K3/0231 , H03K3/0322
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译： 集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。 改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。
-
公开(公告)号：US20110122721A1
公开(公告)日：2011-05-26
申请号：US13013592
申请日：2011-01-25
IPC分类号： G11C8/10
CPC分类号： G11C8/10
摘要： A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage.
摘要翻译： Y解码器包括选择单元和Y-MUX。 选择单元耦合到用于选择列线的存储器阵列。 Y-MUX耦合到选择单元，用于向所选择的列线提供电压。 Y-MUX包括并联耦合的第一开关，第二开关，第三开关和第四开关。 第一开关和第二开关分别用于接收第一屏蔽电压和第二屏蔽电压。 第三开关和第四开关分别用于接收第一感测电压和第二感测电压。
-
公开(公告)号：US20110087838A1
公开(公告)日：2011-04-14
申请号：US12577891
申请日：2009-10-13
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5642 , G11C2211/5647
摘要： Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit.
摘要翻译： 提供了一种MLC（多级单元）存储器件，包括：存储器阵列，包括多个组，每组存储多个位; 以及反比特存储部，存储包括多个反比特的第一反比特数据，存储器阵列中的同一组中的多个比特与相应的反比特相关。
-
公开(公告)号：US09147480B2
公开(公告)日：2015-09-29
申请号：US13328010
申请日：2011-12-16
摘要： The configurations of sense amplifier and methods thereof are provided. The proposed sense amplifier includes a switch circuit having a main control switch, a sensing switch and a holding switch, wherein the three switches have a first bias, a second bias and a third bias respectively, and an auxiliary control switch electrically connected to the holding switch to control an operation of the holding switch.
摘要翻译： 提供了读出放大器的结构及其方法。 所提出的感测放大器包括具有主控开关，感测开关和保持开关的开关电路，其中三个开关分别具有第一偏压，第二偏压和第三偏压，以及辅助控制开关，电连接到保持 切换到控制保持开关的操作。
-
公开(公告)号：US08780641B2
公开(公告)日：2014-07-15
申请号：US13402327
申请日：2012-02-22
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/00 , G11C29/021 , G11C29/028 , G11C29/42 , G11C2211/5634
摘要： A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group.
摘要翻译： 存储器阵列的特征在于阈值定义，其包括表示由存储器阵列的一部分存储的数据值的阈值电压范围，以及分离阈值电压范围的一组感测窗口。 响应于程序操作和擦除操作中的至少一个，阈值定义是变化的。 这样的操作改变存储在存储器组中的数据值的分布。
-
26.发明申请Method and Apparatus for Adjusting Drain Bias of A Memory Cell With Addressed and Neighbor Bits 有权用于调整具有上位和相邻位的存储单元的漏极偏置的方法和装置公开(公告)号：US20130208552A1
公开(公告)日：2013-08-15
申请号：US13372135
申请日：2012-02-13
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C2211/5621
摘要： The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.
摘要翻译： 诸如非易失性存储单元的氮化物层的存储层具有存储单独可寻址数据的两个存储部分，通常分别靠近源极端子和漏极端子。 在感测一个存储部件的数据时所施加的漏极电压取决于存储在另一个存储部分的数据。 如果存储在另一个存储部分的数据由超过最小阈值电压的阈值电压表示，则所施加的漏极电压升高。 该技术在读取操作和程序验证操作中有助于拓宽阈值电压窗口。
-
27.发明授权Memory Program Discharge Circuit of bit lines with multiple discharge paths 有权具有多个放电路径的位线的存储器程序放电电路公开(公告)号：US08358550B2
公开(公告)日：2013-01-22
申请号：US12769502
申请日：2010-04-28
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/06 , G11C16/24 , G11C16/26 , Y10T29/49117
摘要： A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation.
摘要翻译： 存储器集成电路具有非易失性存储单元的阵列，访问非易失性存储单元阵列的位线和位线放电电路。 在编程操作期间，位线在同一时间对于位线具有多个放电路径。
-
公开(公告)号：US08164953B2
公开(公告)日：2012-04-24
申请号：US13041642
申请日：2011-03-07
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C8/08 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely.
摘要翻译： 在其中提供存储器及其操作方法。 当搜索存储器的阈值电压分布的边界时，将校正由存储器的尾部位产生的数据错误。 因此，感测窗口可以更宽，并且可以精确地确定阈值电压分布的边界。
-
公开(公告)号：US07961027B1
公开(公告)日：2011-06-14
申请号：US12631661
申请日：2009-12-04
IPC分类号： G06F1/04
CPC分类号： H03K3/13 , H03K3/011 , H03K3/0231 , H03K3/0322
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译： 集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。 改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。
-
公开(公告)号：US20110019456A1
公开(公告)日：2011-01-27
申请号：US12508607
申请日：2009-07-24
IPC分类号： G11C7/02
摘要： A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node.
摘要翻译： 感测放大器包括感测节点，参考节点，存储器输入级电路，参考输入级电路，输出级电路和屏蔽电路。 存储器输入级电路包括用于维持由单元电流建立的第一感测电压的第一输入节点，并响应于第一感测电压在感测节点上建立第二感测电压。 参考输入级电路包括输出节点和第二输入节点，其用于维持由参考电流建立的第一参考电压，并响应于第一参考电压在参考节点上建立第二参考电压。 输出级电路响应于第二参考电压和第二感测电压获得感测结果。 第一屏蔽电路屏蔽输出节点不受参考节点上的第二参考电压的干扰。
-
-
-
-
-
-
-
-
-
搜索结果
107 条记录 (耗时 0.026 秒)
