Modular power supply architecture optimized for flat efficiency across loadings

    公开(公告)号:US11777394B1

    公开(公告)日:2023-10-03

    申请号:US17724985

    申请日:2022-04-20

    CPC classification number: H02M1/0048 H02M1/0043

    Abstract: A control method improves the efficiency profile of a power supply across a wide range of output loading. The method includes obtaining a measure of output power for a power supply, which includes one or more output modules and an auxiliary power supply. The method determines whether a maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power. Responsive to a determination that the maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power, the controller of the power supply directs the auxiliary power supply to provide the output power.

    FAULT MANAGED POWER WITH DYNAMIC AND ADAPTIVE FAULT SENSOR

    公开(公告)号:US20230223988A1

    公开(公告)日:2023-07-13

    申请号:US18187006

    申请日:2023-03-21

    CPC classification number: G06F1/305

    Abstract: Techniques are provided for detecting a fault across a pair of lines. Pulse power is applied across the pair of lines. The pulse power comprises alternating pulse on-time intervals and pulse off-time intervals. During a pulse off-time interval, a resistor is connected across the pair of lines and then disconnected when a voltage across the pair of lines reaches a first droop percentage in a first period of time. After disconnecting the resistor, it is determined whether the voltage across the pair of lines droops at least a second droop percentage within a second period of time that begins after the first period of time. Occurrence of a line-to-line fault across the pair of lines is determined when the voltage across the pair of lines droops by at least the second droop percentage or more within the second period of time.

    Three-phase AC load unbalance detection and balancing method and circuit

    公开(公告)号:US11682904B2

    公开(公告)日:2023-06-20

    申请号:US17484847

    申请日:2021-09-24

    CPC classification number: H02J3/26 G01R29/16

    Abstract: A method comprises, at a power balancing circuit for three-phase AC power: feeding three power phases to respective loads; measuring power drain on the three power phases by the respective loads; based on measuring, detecting an unbalanced power drain across the three power phases due to a relatively light power drain on one or more lightly loaded power phases and a relatively high power drain on one or more heavily loaded power phases; computing an amount of power to be drained from the one or more lightly loaded power phases and to be fed to the one or more heavily loaded power phases to balance the power drain across the three power phases; and transferring the amount of power from the one or more lightly loaded power phases to the one or more heavily loaded power phases to balance the power drain across the three power phases.

    Battery charging cut-off circuit
    27.
    发明授权

    公开(公告)号:US11342762B2

    公开(公告)日:2022-05-24

    申请号:US17097611

    申请日:2020-11-13

    Abstract: In one embodiment, a battery backup unit (BBU) cut-off and recharge circuit includes: a first transistor, a power entry connection connected to a main power supply, where power from the power entry connection flows to application circuits for an electronic device, and the first transistor is positioned between a BBU and the power entry connection, and a microcontroller, where the microcontroller is operative to: detect a loss of power from the main power supply, turn on the first transistor to enable the BBU to discharge through the power entry connection to application circuits, detect a status of charge (SOC) for the BBU, and upon detecting that the SOC is under a predefined threshold, set the BBU cut-off and recharge circuit to a lockdown state by turning off the first transistor.

    Hot swap inrush current limiter circuit

    公开(公告)号:US10971923B2

    公开(公告)日:2021-04-06

    申请号:US16113655

    申请日:2018-08-27

    Abstract: In one embodiment, a hot swap inrush current limiter circuit includes a pair of paths connecting an input and a load, a first capacitor connected in series with a switch between the paths, a first resistor connected to one of the paths and to a junction between the switch and the first capacitor, a second capacitor connected in series with a second resistor between the paths, with a gate of the switch connected to a junction between the second capacitor and the second resistor, a first diode connected in parallel with the second capacitor, and a second diode connected in parallel with the second resistor to allow for discharge of the second capacitor when input power is off. A method is also disclosed herein.

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