公开(公告)号：US20120045873A1

公开(公告)日：2012-02-23

申请号：US12859644

申请日：2010-08-19

Applicant: Yong-Kuk Jeong ,  Laegu Kang ,  Kim Nam Sung ,  Dae-won Yang

Inventor： Yong-Kuk Jeong ,  Laegu Kang ,  Kim Nam Sung ,  Dae-won Yang

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/28255 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7843

Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.

Abstract translation: 形成集成电路器件的方法包括形成其中具有SiGe沟道区的PMOS晶体管，然后将至少一部分PMOS晶体管暴露于氢等离子体。 可以在PMOS晶体管上形成拉伸应力层。 曝光步骤可以包括将PMOS晶体管的源极和漏极区域暴露于氢等离子体。

公开(公告)号：US07126172B2

公开(公告)日：2006-10-24

申请号：US10962944

申请日：2004-10-12

Applicant: Sangwoo Lim ,  Laegu Kang ,  Geoffrey (Choh-Fei) Yeap

Inventor： Sangwoo Lim ,  Laegu Kang ,  Geoffrey (Choh-Fei) Yeap

IPC: H01L29/80 ,  H01L31/112

CPC classification number: H01L21/823462

Abstract: A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.

公开(公告)号：US20060079047A1

公开(公告)日：2006-04-13

申请号：US10962944

申请日：2004-10-12

Applicant: Sangwoo Lim ,  Laegu Kang ,  Geoffrey Yeap

Inventor： Sangwoo Lim ,  Laegu Kang ,  Geoffrey Yeap

IPC: H01L21/8238 ,  H01L21/31

CPC classification number: H01L21/823462

Abstract: A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate (203) having a sacrificial oxide layer (207) thereon; (b) depositing and patterning a first layer of photoresist (209) on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer (211) within the first etched region; (e) depositing and patterning a second layer of photoresist (213) on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer (215) within the second etched region.

Abstract translation: 提供多栅极氧化工艺。 该方法包括以下步骤：（a）提供其上具有牺牲氧化物层（207）的硅衬底（203）; （b）在所述牺牲氧化物层上沉积和图案化第一层光致抗蚀剂（209），从而形成其中暴露所述牺牲氧化物层的第一区域; （c）蚀刻第一区域内的暴露的牺牲氧化物层，由此形成第一蚀刻区域; （d）在第一蚀刻区域内生长第一氧化物层（211）; （e）在所述牺牲氧化物层和所述第一氧化物层上沉积和图案化第二层光致抗蚀剂（213），从而形成其中暴露所述牺牲氧化物层的第二区域; （f）蚀刻第二区域内的暴露的牺牲氧化物层，从而形成第二蚀刻区域; 和（g）在第二蚀刻区域内生长第二氧化物层（215）。

公开(公告)号：US06724048B2

公开(公告)日：2004-04-20

申请号：US10462178

申请日：2003-06-16

Applicant: Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

Inventor： Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

IPC: H01L2100

CPC classification number: H01L29/42384 ,  H01L29/7841

Abstract: An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Abstract translation: 使用绝缘体上硅（SOI）的集成电路的大多数晶体管的通道（体）浮动。 然而，一些晶体管必须使其沟道耦合到预定的偏压，以便实现期望的操作特性。 为了获得所需的偏置，在SOI衬底的半导体层中和在晶体管的栅极的延伸下提供接触路径。 该延伸部分通过绝缘体与半导体层分离，该绝缘体比大多数晶体管的绝缘体更厚，但有利地与用于一般用于高电压应用的一些厚栅极绝缘体器件相同。 这种较厚的绝缘体有利地减小电容，但是不会增加工艺的复杂性，因为它使用了该工艺已经需要的绝缘体。

公开(公告)号：US06620656B2

公开(公告)日：2003-09-16

申请号：US10024916

申请日：2001-12-19

Applicant: Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

Inventor： Byoung W. Min ,  Michael A. Mendicino ,  Laegu Kang

IPC: H01L2100

CPC classification number: H01L29/42384 ,  H01L29/7841

Abstract: An integrated circuit using silicon-on-insulator (SOI) has most of its transistors with their channels (bodies) floating. Some of the transistors, however, must have their channels coupled to a predetermined bias in order to achieve desired operating characteristics. In order to achieve the needed bias, a contact path is provided in the semiconductor layer of the SOI substrate and under an extension of the gate of the transistor. The extension is separated from the semiconductor layer by an insulator that is thicker than that for most of the transistor but advantageously is the same as that used for some of the thick gate insulator devices used, typically, for high voltage applications. This thicker insulator advantageously reduces the capacitance, but does not increase process complexity because it uses an insulator already required by the process.

Abstract translation: 使用绝缘体上硅（SOI）的集成电路的大多数晶体管的通道（体）浮动。 然而，一些晶体管必须使其沟道耦合到预定的偏压，以便实现期望的操作特性。 为了获得所需的偏置，在SOI衬底的半导体层中和在晶体管的栅极的延伸下提供接触路径。 该延伸部分通过绝缘体与半导体层分离，该绝缘体比大多数晶体管的绝缘体更厚，但有利地与用于一般用于高电压应用的一些厚栅极绝缘体器件相同。 这种较厚的绝缘体有利地减小电容，但是不会增加工艺的复杂性，因为它使用了该工艺已经需要的绝缘体。