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公开(公告)号：US11221710B2
公开(公告)日：2022-01-11
申请号：US16612998
申请日：2019-02-28
Inventor： Qiujie Su
Abstract: A shift register unit includes a first pull-up node control circuit, a second pull-up node control circuit, a pull-down node control circuit, an output pull-up circuit and an output pull-down circuit. The first pull-up node control circuit is configured to control a first pull-up node to be electrically connected to a second voltage end under the control of an input signal, and control the first pull-up node to be electrically connected to a first voltage end under the control of a resetting signal and/or a voltage signal at a pull-down node. The second pull-up node control circuit is configured to control a second pull-up node to be electrically connected to an input end under the control of the input signal, and control the second pull-up node to be electrically connected to the first voltage end under the control of the resetting signal.
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22.发明申请公开(公告)号：US20180047356A1
公开(公告)日：2018-02-15
申请号：US15652493
申请日：2017-07-18
Inventor： Qiujie Su
CPC classification number: G09G3/3648 , G09G3/3614 , G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0286 , G09G2310/061 , G11C19/28 , G11C19/287
Abstract: The embodiments of the present disclosure provide a shift register unit, a method for driving the shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises a first input module, a first output module, a first reset module, a first storage module and a second reset module. The first input module is configured to output a first pull-up signal to the first output module based on a first input signal. The first output module is configured to output an output signal based on the first pull-up signal and a first clock signal. The first storage module is configured to store the first pull-up signal. The first reset module is configured to reset the first storage module based on a first reset signal. The second reset module is configured to reset the output from the first output module based on a second reset signal. The second reset signal is set to be valid while the first pull-up signal and the first clock signal are valid and a duration in which the second reset signal is valid is shorter than a duration in which the first clock signal is valid.
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公开(公告)号：US12236912B2
公开(公告)日：2025-02-25
申请号：US17915712
申请日：2021-10-28
Inventor： Yanping Liao , Yingmeng Miao , Seungmin Lee , Xibin Shao , Shulin Yao , Yinlong Zhang , Qiujie Su , Cong Wang , Dongchuan Chen , Jiantao Liu
IPC: G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.
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公开(公告)号：US12159878B2
公开(公告)日：2024-12-03
申请号：US17637485
申请日：2021-03-26
Inventor： Qiujie Su , Zhihua Sun , Tao Yang , Dongchuan Chen , Yingmeng Miao , Jiantao Liu , Seungmin Lee
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L27/12
Abstract: The present disclosure relates to an array substrate and a display device. The array substrate may include: a first substrate, and a plurality of pixel groups and a plurality of columns of data lines formed on the first substrate; wherein the plurality of pixel groups are arranged in an array along a row direction and a column direction, and each pixel group includes two sub-pixels arranged in the row direction; at least one sub-pixel of one of any two adjacent pixel groups in the row direction corresponds to the same color as one sub-pixel of the other pixel group; and any two adjacent sub-pixels in the row direction correspond to different colors; and each column of data line and each column of pixel groups are alternately arranged in the row direction.
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公开(公告)号：US12107073B2
公开(公告)日：2024-10-01
申请号：US17429929
申请日：2020-10-27
Inventor： Zhihua Sun , Yanping Liao , Seungmin Lee , Qiujie Su , Feng Qu , Yingmeng Miao , Xibin Shao
IPC: H01L25/065 , H01L25/00 , H01L23/12
CPC classification number: H01L25/0655 , H01L25/50 , H01L23/12
Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.
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Patent Agency Ranking
公开(公告)号：US12039907B2
公开(公告)日：2024-07-16
申请号：US18457637
申请日：2023-08-29
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1
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公开(公告)号：US11921388B2
公开(公告)日：2024-03-05
申请号：US17792264
申请日：2021-09-01
Inventor： Wenjie Hou , Yingmeng Miao , Qiujie Su , Chongyang Zhao , Feng Qu
IPC: G02F1/1362
CPC classification number: G02F1/136286 , G02F1/136209 , G02F1/136222
Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate comprises a plurality of data lines and sub-pixels. At least one sub-pixel comprises: a first insulating layer; a gate; an active layer located on one side of the first insulating layer away from the gate; a pixel electrode; a first electrode located connected to the active layer and in contact with the pixel electrode; a second electrode connected to the active layer and a data line; a second insulating layer having a first opening, wherein the orthographic projection of the first opening partially overlaps with the orthographic projections of the pixel electrode and the first electrode; a connection electrode in contact with the pixel electrode and the first electrode through the first opening; and a common electrode located on one side of the second insulating layer away from the pixel electrode.
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公开(公告)号：US20210405488A1
公开(公告)日：2021-12-30
申请号：US16765940
申请日：2019-06-28
Inventor： Qiujie Su , Xibin Shao
IPC: G02F1/1362 , G02F1/1368
Abstract: The present disclosure provides a display substrate and a liquid crystal panel. The display substrate includes: a substrate; and a common electrode and a pixel electrode array layer which are located on a side of the substrate and are spaced by insulation, wherein the common electrode includes a transparent conductive layer; the pixel electrode array layer includes a plurality of pixel electrode groups arranged in a column direction, wherein each of the pixel electrode groups includes two rows of pixel electrodes, two gate lines extending along a row direction and arranged in the column direction is provided between two adjacent pixel electrode groups, and each of the gate lines is connected to a plurality of thin film transistors, each of the pixel electrodes is connected to one of the thin film transistors; an orthographic projection of a gap, which is between two pixel electrodes adjacent in the column direction of the pixel electrode group, on the substrate falls within an orthographic projection of the common electrode on the substrate.
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公开(公告)号：US20210074774A1
公开(公告)日：2021-03-11
申请号：US17016511
申请日：2020-09-10
Inventor： Qiujie Su , Zhihua Sun
IPC: H01L27/32
Abstract: The embodiments of the present disclosure provide a display panel and a display apparatus. The display panel includes: a first substrate; a plurality of sub-pixels arranged in an array on the substrate, the plurality of sub-pixels comprising a first type of sub-pixels and a second type of sub-pixels; and at least one data line, each of which is disposed between adjacent columns of sub-pixels of the array and extending along a second direction, an overlapped area of projection of each data line on the first substrate and projection of the first type of sub-pixels on the first substrate has a first width, and an overlapped area of the projection of each data line on the first substrate and projection of the second type of sub-pixels on the first substrate has a second width less than the first width.
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公开(公告)号：US10170068B2
公开(公告)日：2019-01-01
申请号：US15519836
申请日：2016-08-30
IPC: G09G3/36 , G06F3/0354
Abstract: The embodiments of the present disclosure provide a gate driving circuit, an array substrate, a display panel and a driving method. The gate driving circuit comprises: at least a Gate driver on Array (GOA) unit GOAn and a GOA unit GOAn+m, an output terminal of GOAn being connected to an input terminal of GOAn+m, an output terminal of GOAn+m is connected to a reset terminal of GOAn; and an electrical leakage compensation module having two input terminals connected to output terminals of GOAn and GOAn+m, respectively, a control terminal connected to a signal line, and an output terminal connected to a Pull-Up (PU) node of GOAn+m, and configured to compensate for a voltage at the PU node of GOAn+m in response to receipt of the electrical leakage compensation signal VLHB. According to the embodiments of the present disclosure, an electrical leakage compensation module is added between two cascaded GOA units for compensating for a voltage decrease due to electrical leakage by charging the GOA unit at the next stage.
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