Phase shift error mitigation for power converters with coupled inductors

    公开(公告)号:US11837960B2

    公开(公告)日:2023-12-05

    申请号:US17483515

    申请日:2021-09-23

    Applicant: Apple Inc.

    CPC classification number: H02M3/1586 H02M1/0003 H02M1/084 H02M3/1584

    Abstract: A power converter circuit that includes multiple phase circuits may employ coupled inductors to generate a particular voltage level on a regulated power supply node. In response to an initiation of an active time period, the phase circuits cycle, out of phase with each other, between on-times and off-times. To maintain the phase relationship between the operation of the phase circuits, each phase circuit generates a ramp current that is compared to the current flowing in its corresponding inductor and then halts an off-time based on a result of the comparison.

    Pulse frequency modulation control methods for multi-phase power converters with coupled inductors

    公开(公告)号:US11736017B2

    公开(公告)日:2023-08-22

    申请号:US17482215

    申请日:2021-09-22

    Applicant: Apple Inc.

    CPC classification number: H02M3/1586 H02M1/0009 H02M3/157

    Abstract: A power converter circuit that includes multiple phase circuits may employ coupled inductors to generate a particular voltage level on a regulated power supply node. Based on a comparison of a voltage level of the regulated power supply node and a reference voltage, the power converter circuit may initiate an active period, during which the phase circuits source respective currents to the regulated power supply node via corresponding coils included in the coupled inductor. After a time period has elapsed following an initiation of the active period, the operation of the phase circuits is adjusted so that the respective currents flowing in the coils of the coupled inductor are out of phase.

    PFM Control Method for Boost Converters

    公开(公告)号:US20210257911A1

    公开(公告)日:2021-08-19

    申请号:US16793516

    申请日:2020-02-18

    Applicant: Apple Inc.

    Abstract: The present disclosure is directed to a pulse frequency modulation (PFM) control method for a boost converter and apparatus for carrying out the method. A boost converter includes an inductor and a transistor coupled thereto. A control circuit is arranged to control the transistor to cause current pulsed to be sourced through the inductor. When operating in a PFM mode, the control circuit may control the timing of pulses such that, at the beginning of a specified time period, current pulses may be sourced with no spacing between successive pulses. After a desired number of pulses have been sourced, no pulses are sourced for the remainder of the specified time period. Nevertheless, the number of pulses sourced over the time period corresponds to a desired average frequency of pulses.

    Phase Reassignment Between Power Converters

    公开(公告)号:US20250112541A1

    公开(公告)日:2025-04-03

    申请号:US18443501

    申请日:2024-02-16

    Applicant: Apple Inc.

    Abstract: Phase reassignment among power converters is disclosed. Multi-phase power converters of a plurality are arranged such that the various phases of each can be shared. When a given power converter has a high demand current and a phase of another power converter in the same group is currently unused, that phase may be borrowed by the given power converter to meet the demand current. The power converter that borrows a phase from another power converter is designated as the leader, while the borrowed phase is designated as a follower. The regulated supply voltage is determined by the leader power converter, irrespective of the regulated output voltage to be generated by the power converter from which another phase is borrowed.

    Power converter circuit for use with multiple low-current power rails

    公开(公告)号:US12231044B2

    公开(公告)日:2025-02-18

    申请号:US18153057

    申请日:2023-01-11

    Applicant: Apple Inc.

    Abstract: A power management circuit for computer systems includes a power converter circuit that generates different voltage levels at different time periods. Multiple voltage regulator circuits are coupled to the output of the power converter circuit and to respective local power supply nodes. Switch devices are used to bypass the voltage regulator circuits during corresponding ones of the different time periods.

    Regulator Switch Array
    26.
    发明申请

    公开(公告)号:US20240396452A1

    公开(公告)日:2024-11-28

    申请号:US18792905

    申请日:2024-08-02

    Applicant: Apple Inc.

    Abstract: A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.

    Power converter with DCR sensing circuit having improved noise immunity

    公开(公告)号:US11949334B2

    公开(公告)日:2024-04-02

    申请号:US17644521

    申请日:2021-12-15

    Applicant: Apple Inc.

    CPC classification number: H02M3/158 H02M1/0009 H02M3/1584

    Abstract: A power converter is disclosed. The power converter includes a switching circuit configured to source current to a switch node that is coupled, via an inductor, to a regulated power supply node. A DC resistance sensing circuit includes a first filter and a second filters. The first filter circuit is configured to filter a voltage level of a first terminal of the inductor to generate a first filtered signal, while the second filter circuit is configured to filter a voltage level of a second terminal of the inductor to generate a second filtered signal. A control circuit is configured to adjust the operation of the switching circuit using a voltage level of the regulated power supply node, the first filtered signal, and the second filtered signal.

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