公开(公告)号：US20130249517A1

公开(公告)日：2013-09-26

申请号：US13692010

申请日：2012-12-03

申请人： Kei SHIRAISHI ,  Takeshi UENO ,  Taichi OGAWA ,  Tetsuro ITAKURA

发明人： Kei SHIRAISHI ,  Takeshi UENO ,  Taichi OGAWA ,  Tetsuro ITAKURA

IPC分类号： G05F1/46

CPC分类号： G05F1/468 ,  H02M3/157 ,  H02M2003/1566

摘要： A control circuit of a DC-DC converter has a voltage difference signal generator configured to generate a digital voltage difference signal depending on a voltage difference between the output voltage and a reference voltage, a PID controller configured to generate a digital PID signal for determining the duty ratio of the pulse-width modulated signal, based on the digital voltage difference signal, a phase controller configured to generate a digital phase control signal for determining a phase of the pulse-width modulated signal, based on the digital voltage difference signal, and a PWM generator configured to generate the pulse-width modulated signal, based on the digital PID signal and the digital phase control signal.

摘要翻译： DC-DC转换器的控制电路具有：电压差信号发生器，被配置为根据输出电压和参考电压之间的电压差产生数字电压差信号; PID控制器，被配置为产生数字PID信号，用于确定 基于数字电压差信号的脉宽调制信号的占空比;相位控制器，被配置为基于数字电压差信号产生用于确定脉宽调制信号的相位的数字相位控制信号;以及 PWM发生器，被配置为基于数字PID信号和数字相位控制信号来产生脉宽调制信号。

公开(公告)号：US08410762B2

公开(公告)日：2013-04-02

申请号：US13306119

申请日：2011-11-29

申请人： Takeshi Ueno ,  Tetsuro Itakura

发明人： Takeshi Ueno ,  Tetsuro Itakura

IPC分类号： G05F1/613 ,  G05F1/40

CPC分类号： H02M3/1588 ,  Y02B70/1466

摘要： The high-side switch has one end connected to the input terminal. The low-side switch has one end connected to other end of the high-side switch and other end connected to a ground terminal. The inductor has one end connected to the other end of the high-side switch and other end connected to the output terminal. The capacitor has one end connected to the other end of the inductor and other end connected to the ground terminal. The high-side switch controlling circuit generates and supplies a high-side switch controlling signal based on a target voltage of the output terminal, the output voltage of the output terminal, and a current flowing through the capacitor, to the high-side switch. The low-side switch controlling circuit generates and supplies a low-side switch controlling signal based on the high-side switch controlling signal and a current flowing through the inductor, to the low-side switch.

摘要翻译： 高边开关的一端连接到输入端。 低侧开关的一端连接到高侧开关的另一端，另一端连接到接地端子。 电感器的一端连接到高侧开关的另一端，另一端连接到输出端子。 电容器的一端连接到电感器的另一端，另一端连接到接地端子。 高侧开关控制电路基于输出端子的目标电压，输出端子的输出电压和流过电容器的电流产生并提供高侧开关控制信号到高侧开关。 低侧开关控制电路基于高侧开关控制信号和流过电感器的电流产生并提供低侧开关控制信号到低侧开关。

公开(公告)号：US08277254B2

公开(公告)日：2012-10-02

申请号：US11988307

申请日：2005-12-22

申请人： Masahiro Yamamoto ,  Takeshi Ueno ,  Kazufumi Oogi ,  Kenichi Yoneyama ,  Hideshi Hamaguchi

发明人： Masahiro Yamamoto ,  Takeshi Ueno ,  Kazufumi Oogi ,  Kenichi Yoneyama ,  Hideshi Hamaguchi

IPC分类号： H01R13/66

CPC分类号： H01R25/006 ,  H01R25/164 ,  H04L12/2803 ,  Y02B70/325 ,  Y04S20/228 ,  Y10T307/406 ,  Y10T307/461

摘要： A dual wiring system with easy exchangeability of a function unit. A gate device is mounted in a wall surface of a structure, and connected to both of an electric power line and an information line previously installed in the structure. The function unit has at least one of functions for supplying electric power from the electric power line, outputting information from the information line and inputting information into the information line when connected with the gate device. The function unit has a module connector including an electric power connector and an information signal connector, which is detachably connected to a module port of the gate device comprised of an electric power port and an information signal port. To further improve function expandability, an additional function unit can be detachably connected to the function unit.

摘要翻译： 具有功能单元易于更换的双重布线系统。 门装置安装在结构的壁表面中，并连接到电力线和预先安装在结构中的信息线。 功能单元具有从电力线提供电力的功能中的至少一种，当与门装置连接时，从信息线输出信息并将信息输入信息线。 功能单元具有包括电力连接器和信息信号连接器的模块连接器，其可拆卸地连接到由电力端口和信息信号端口构成的门装置的模块端口。 为了进一步提高功能扩展性，附加功能单元可以可拆卸地连接到功能单元。

公开(公告)号：US07532144B2

公开(公告)日：2009-05-12

申请号：US12104488

申请日：2008-04-17

申请人： Takafumi Yamaji ,  Takeshi Ueno

发明人： Takafumi Yamaji ,  Takeshi Ueno

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/44 ,  H03M1/46

摘要： Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n≦m≦2n), a decoding part to generate m pieces of decoded analog signals from the m parallel pieces of quantized signals, and a residual amplifying part to output m pieces of amplified residual signals by multiplying respective differences between each of the m pieces of analog signals and each of the m pieces of decoded analog signals; a second conversion stage including a quantizing part to generate m parallel pieces of quantized signals from the m pieces of amplified residual signals; and a synthesizing part to generate m parallel pieces of digital signals by synthesizing each of the quantized signals in the first conversion stage and in the second conversion stage at each parallel position.

摘要翻译： 公开了一种AD转换器，包括：第一转换级，包括量化部分，用于从表示n维向量（n <= m <= 2n）的m个输入模拟信号生成m个并行量化信号，生成 m个来自m个并行量化信号的解码模拟信号，以及残余放大部分，通过将m个模拟信号中的每一个与m个解码模拟信号中的每一个相乘来输出m个放大残差信号 信号; 第二转换级，包括从所述m个放大残差信号中产生m个并行量化信号的量化部分; 以及通过在每个平行位置合成第一转换级和第二转换级中的每个量化信号来产生m个并行数字信号的合成部分。

公开(公告)号：US20090079598A1

公开(公告)日：2009-03-26

申请号：US12057647

申请日：2008-03-28

申请人： Masanori Furuta ,  Takafumi Yamaji ,  Takeshi Ueno

发明人： Masanori Furuta ,  Takafumi Yamaji ,  Takeshi Ueno

IPC分类号： H03M7/00

CPC分类号： H03H17/04 ,  H03H17/0416

摘要： The sample rate converter includes a synthesizing unit which synthesizes an input signal sampled with frequency fs with a feedback signal of the frequency fs, in a frequency band from 0 to fs/N (where N indicates a natural number), with a gain greater than at least 1, to generate a synthesized signal, a downsampler which downsamples the synthesized signal to obtain an output signal of sample rate fs/N, and an upsampler which upsamples the output signal to generate the feedback signal.

摘要翻译： 采样率转换器包括合成单元，其将从频率fs采样的输入信号与频率fs的反馈信号在0至fs / N（其中N表示自然数）的频带中合成，增益大于 至少1，以产生合成信号，下采样器，其对合成信号进行下采样以获得采样率fs / N的输出信号;以及上采样器，其对输出信号进行采样以产生反馈信号。

公开(公告)号：US20090045995A1

公开(公告)日：2009-02-19

申请号：US12175209

申请日：2008-07-17

申请人： Mai NOZAWA ,  Daisuke Kurose ,  Takeshi Ueno ,  Tetsuro Itakura

发明人： Mai NOZAWA ,  Daisuke Kurose ,  Takeshi Ueno ,  Tetsuro Itakura

IPC分类号： H03M1/34

CPC分类号： H03K5/2481 ,  H03K5/249

摘要： A comparator includes a first inverter which is inserted between a power source terminal and one end of a first variable resistor, includes a first FinFET provided with a first gate terminal for receiving a positive phase output signal, and a second gate terminal for receiving a clock signal changing between a first level and a second level, inverts the positive phase output signal, and outputs a negative phase output signal, and a second inverter which is inserted between the power source terminal and one end of a second variable resistor, includes a second FinFET provided with a third gate terminal for receiving the negative phase output signal, a fourth gate terminal for receiving the clock signal, and the same polarity as the first FinFET, inverts the negative phase output signal, and outputs the positive phase output signal.

摘要翻译： 比较器包括插入在电源端子和第一可变电阻器的一端之间的第一反相器，包括：第一FinFET，其具有用于接收正相输出信号的第一栅极端子和用于接收时钟的第二栅极端子 信号在第一电平和第二电平之间变化，使正相输出信号反相，并输出负相输出信号，并且插入在电源端和第二可变电阻的一端之间的第二反相器包括第二 FinFET具有用于接收负相输出信号的第三栅极端子，用于接收时钟信号的第四栅极端子和与第一FinFET相同的极性，反相负相输出信号，并输出正相输出信号。

公开(公告)号：US07379009B2

公开(公告)日：2008-05-27

申请号：US11623803

申请日：2007-01-17

申请人： Takafumi Yamaji ,  Takeshi Ueno

发明人： Takafumi Yamaji ,  Takeshi Ueno

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/44 ,  H03M1/46

摘要： Disclosed is an AD converter including: a first conversion stage including a quantizing part to generate m parallel pieces of quantized signals from m pieces of input analog signals representing n-dimensional vectors (n

摘要翻译： 公开了一种AD转换器，包括：第一转换级，包括量化部分，用于从表示n维向量（n

公开(公告)号：US07352310B2

公开(公告)日：2008-04-01

申请号：US11753819

申请日：2007-05-25

申请人： Hiroki Mori ,  Takeshi Ueno ,  Kazumi Sato

发明人： Hiroki Mori ,  Takeshi Ueno ,  Kazumi Sato

IPC分类号： H03M1/62

CPC分类号： H03M1/185

摘要： A receiving device includes a receiver; a frequency converter; an A/D converter; and a digital signal processor, wherein the A/D converter includes a variable gain amplifier adjusting a signal level of the analog signal from the frequency converter; an A/D converting portion converting an analog signal from the variable gain amplifier into an m-bit digital signal and an n-bit digital signal and outputting the m-bit digital signal and the n-bit digital signal, the n-bit digital signal serving as an output signal to the digital signal processor; and a gain controller calculating a coarse adjustment gain of the variable gain amplifier on the basis of a power of the m-bit digital signal to control the gain of the variable gain amplifier and calculating a fine adjustment gain on the basis of a power of the n-bit digital signal to control the gain of the variable gain amplifier.

摘要翻译： 接收装置包括接收机; 变频器; A / D转换器; 以及数字信号处理器，其中所述A / D转换器包括调节来自所述变频器的模拟信号的信号电平的可变增益放大器; A / D转换部分将来自可变增益放大器的模拟信号转换为m位数字信号和n位数字信号，并输出m位数字信号和n位数字信号，n位数字信号 信号作为数字信号处理器的输出信号; 以及增益控制器，其基于所述m位数字信号的功率，计算所述可变增益放大器的粗调增益，以控制所述可变增益放大器的增益，并且基于所述可变增益放大器的功率计算微调整增益 n位数字信号来控制可变增益放大器的增益。

公开(公告)号：US20070011482A1

公开(公告)日：2007-01-11

申请号：US11438589

申请日：2006-05-22

申请人： Akihide Sai ,  Takeshi Ueno ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Akihide Sai ,  Takeshi Ueno ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： G06F1/00

CPC分类号： H03L7/23 ,  H03L7/18

摘要： A clock generator having phase locked loops to receive reference signals from a shared reference signal source and generate clock signals differing in frequency, respectively, includes a phase comparator which generates a voltage signal in response to a phase difference between a phase of the reference signal and a phase of a feedback signal, a VCO controlled by a voltage signal from the phase comparator, and a frequency divider group connected in cascade in a feedback loop between an output of the VCO and an input of a feedback signal, and takes out a clock signals from each output of the frequency divider group.

摘要翻译： 具有锁相环的时钟发生器分别接收来自共享参考信号源的参考信号并且分别产生频率不同的时钟信号，该相位比较器响应于参考信号的相位和相位差之间的相位差产生电压信号 反馈信号的相位，由来自相位比较器的电压信号控制的VCO和在VCO的输出与反馈信号的输入之间的反馈回路中级联连接的分频器组，并且取出时钟 来自分频器组的每个输出的信号。

公开(公告)号：US06995118B2

公开(公告)日：2006-02-07

申请号：US10674171

申请日：2003-09-29

申请人： Takeshi Ueno ,  Katsuyuki Oshima ,  Mikio Asajima ,  Mineo Yamauchi ,  Kazunobu Imoto ,  Hidetake Takahara ,  Jitsuhiko Ando

发明人： Takeshi Ueno ,  Katsuyuki Oshima ,  Mikio Asajima ,  Mineo Yamauchi ,  Kazunobu Imoto ,  Hidetake Takahara ,  Jitsuhiko Ando

IPC分类号： B41M5/035 ,  B41M5/38

CPC分类号： B41M5/42 ,  B41M5/40 ,  B41M5/41 ,  B41M5/423 ,  B41M5/426 ,  B41M5/44 ,  B41M5/46 ,  B41M5/52 ,  B41M5/5218 ,  B41M5/5227 ,  B41M5/5245 ,  B41M5/5254 ,  B41M5/5272 ,  B41M5/529 ,  B41M7/0027 ,  B41M2205/02 ,  B41M2205/32 ,  B41M2205/38 ,  Y10S428/913 ,  Y10S428/914 ,  Y10T156/1051 ,  Y10T428/24934 ,  Y10T428/249953 ,  Y10T428/31993

摘要： Disclosed is a thermal transfer image receiving sheet comprising a substrate sheet, an intermediate layer provided on at least one surface side of the substrate sheet and a dye receptor layer provided on the surface of the intermediate layer, wherein the substrate sheet is a pulp paper, the intermediate layer is formed from an organic solvent solution of a resin, and the dye receptor layer is formed from an aqueous resin liquid. By virtue of this structure, the thermal transfer image receiving sheet can be prevented from occurrence of curling caused by temperature change. Also disclosed is a thermal transfer image receiving sheet comprising a substrate sheet, an intermediate layer provided on at least one surface side of the substrate sheet and a dye receptor layer provided on the surface of the intermediate layer, wherein the intermediate layer is formed from either an acrylic resin or a resin at least a part of which is crosslinked. By virtue of this structure, the thermal transfer image receiving sheet can be excellent in smoothness, strength, cushioning properties and writing properties, and further can give an image of high density and high resolution.