公开(公告)号：US07251756B2

公开(公告)日：2007-07-31

申请号：US10908033

申请日：2005-04-26

申请人： Darren Lane Anand ,  Michael Richard Ouellette ,  Michael Anthony Ziegerhofer

发明人： Darren Lane Anand ,  Michael Richard Ouellette ,  Michael Anthony Ziegerhofer

IPC分类号： G11C29/00

CPC分类号： G11C17/165 ,  G11C29/027 ,  G11C29/4401 ,  G11C29/72

摘要： Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.

摘要翻译： 测试集成电路存储器以发现有缺陷的存储器元件。 为了更换有缺陷的存储器元件，选择备用存储器元件，并且生成字符串以指示哪些备用件替换有缺陷存储器元件中的哪一个。 字符串的位数取决于多少存储器元件有缺陷。 尽管一定数量的存储器元件是有缺陷的，这确定了串比特的数目，然而，确定集成电路上编程的多个保险丝的响应是相对于二进制数的编号有多少个熔丝可用于编程 字符串位。 也就是说，如果比相对于字符串位数（优选的）更多的保险丝可用于某个阈值数，则多于阈值编号。 如果没有，那么只有该阈值数量的保险丝被编程。

公开(公告)号：US5710742A

公开(公告)日：1998-01-20

申请号：US440285

申请日：1995-05-12

申请人： Eric Lee Carter ,  Roger Paul Gregor ,  Moon Ho Lee ,  Michael Richard Ouellette

发明人： Eric Lee Carter ,  Roger Paul Gregor ,  Moon Ho Lee ,  Michael Richard Ouellette

IPC分类号： G11C8/16 ,  G11C11/412 ,  G11C11/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well.

摘要翻译： 双端口存储单元设计允许同时读取和写入在同一字线上但不同位选择行上的单元，而不增加读取访问时间，同时在低电压下保持存储器功能。 存储单元使用标准6晶体管设计来提供用于快速存取的差分读取，并且另外三个晶体管被添加到每个单元以提供差分写入单元的手段，并且如果位选择不活动则解除写入。 该单元设计也适用于多端口存储器。