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21.发明授权Programming the behavior of individual chips or strata in a 3D stack of integrated circuits 有权对集成电路的3D堆叠中的单个芯片或层的行为进行编程公开(公告)号：US08928350B2
公开(公告)日：2015-01-06
申请号：US13607020
申请日：2012-09-07
IPC分类号： H03K19/173 , G01R31/3185 , H01L25/065
CPC分类号： G01R31/318558 , G01R31/318513 , G01R31/318572 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.
摘要翻译： 在具有两个或多个层的3D芯片堆栈中提供了层次管理器。 层管理器包括多个可扫描配置寄存器，每个配置寄存器布置在两个或更多个层中的相应一个上，用于存储一组位。 该组比特被配置为对存储有该组比特的两个或更多个层中的对应的一个或其上的装置的操作进行编程。 此外，还提供了3D堆栈内的3D堆栈和堆栈扫描电路内的层标识符。
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公开(公告)号：US20130049824A1
公开(公告)日：2013-02-28
申请号：US13217349
申请日：2011-08-25
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
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公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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24.发明授权Method and system for restoring register mapper states for an out-of-order microprocessor 失效用于恢复无序微处理器的寄存器映射器状态的方法和系统公开(公告)号：US07689812B2
公开(公告)日：2010-03-30
申请号：US11674754
申请日：2007-02-14
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。
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25.发明申请Using a Register File as Either a Rename Buffer or an Architected Register File 审中-公开使用注册文件作为重命名缓冲区或建筑注册表文件公开(公告)号：US20080244242A1
公开(公告)日：2008-10-02
申请号：US11695303
申请日：2007-04-02
IPC分类号： G06F7/38
CPC分类号： G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885
摘要： A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor is operating. Responsive to determining the thread mode, the instruction dispatch unit determines an ability to use the set of architected register files as the set of temporary rename buffers. Responsive to the ability to use the set of architected register files as the set of temporary rename buffers, the instruction dispatch unit analyzes the instruction to determine an address of an architected register file in the set of architected register files where the instruction data is to be stored. The architected register file operating as a temporary rename buffer stores the instruction data as finished data.
摘要翻译： 提供了一种计算机实现的方法，装置和计算机可用程序代码，用于将一组架构化的寄存器文件实现为一组临时重命名缓冲器。 指令分配单元接收包括指令数据的指令。 指令调度单元确定处理器在其下操作的线程模式。 响应于确定线程模式，指令分派单元确定使用一组架构化寄存器文件作为临时重命名缓冲器集合的能力。 响应于使用该组建筑寄存器文件作为一组临时重命名缓冲器的能力，指令分派单元分析该指令以确定在该指令数据将被设置的一组架构化寄存器文件集中的架构化寄存器文件的地址 存储。 作为临时重命名缓冲区运行的架构化寄存器文件将指令数据存储为完成的数据。
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公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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