公开(公告)号：US5394295A

公开(公告)日：1995-02-28

申请号：US68150

申请日：1993-05-28

Applicant: John Galvagni ,  Sonja Brown ,  Kevin Christian ,  Yong-Jian Qui

Inventor： John Galvagni ,  Sonja Brown ,  Kevin Christian ,  Yong-Jian Qui

IPC: H01G9/00 ,  H01G9/15 ,  H01G1/005

CPC classification number: H01G9/15 ,  H01G11/56 ,  Y02E60/13 ,  Y10T29/417 ,  Y10T29/435

Abstract: A method of manufacturing solid state capacitors involves providing an elongate band of solid state forming metal, folding the band into a trough-like U-shaped configuration, introducing a layer of solid state metal powder into the trough, sintering the powdered metal to thereby bond the metal to the foil, partially severing the foil and sintered powder to define a multiplicity of individual units which are thereafter processed to convert the units into capacitors by sequential dielectric forming and counterelectrode depositing steps. The individual capacitors are terminated and preferably also may be tested while still interconnected by portions of the foil, following which individual capacitors are separated by cuts which register with the initial cuts which defined the individual units. The disclosure further teaches a novel solid state capacitor fabricated in accordance with the method, the capacitor exhibiting high volumetric efficiency and being particularly adapted for surface mounting.

Abstract translation: 制造固态电容器的方法包括提供固态成形金属的细长带，将带折叠成槽状的U形构造，将一层固态金属粉末引入槽中，烧结粉末金属从而结合 金属到箔，部分地切断箔和烧结粉末以限定多个单独的单元，然后通过顺序电介质形成和反电极沉积步骤将单元转换成电容器。 单独的电容器被端接，并且优选地也可以被测试，同时仍然通过箔的部分互连，随后单独的电容器通过与限定各个单元的初始切割对齐的切口分开。 本发明进一步教导了根据该方法制造的新型固态电容器，该电容器具有高体积效率并且特别适用于表面安装。

公开(公告)号：US5341009A

公开(公告)日：1994-08-23

申请号：US90978

申请日：1993-07-09

Applicant: Dennis C. Young ,  Rex E. Lowther

Inventor： Dennis C. Young ,  Rex E. Lowther

IPC: H01L27/11 ,  H01L27/12 ,  H01L29/94 ,  H01L27/02 ,  H01G1/005

CPC classification number: H01L29/94 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12

Abstract: Depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage. An application of the MOS capacitor structure is its use in a single event upset immune memory cell formed on an insulating substrate. A pair of MOS capacitors having a structural configuration in accordance with the present invention are coupled between input and output nodes of a pair of cross-coupled MOSFET inverters that form the memory cell.

Abstract translation: 通过用一对相反导电型，高杂质浓度区域增加MOS电容器结构，两者都直接连续地消除了在轻掺杂半导体材料上形成的常规MOS电容器结构的消耗层深度和半导体空间占用面积的缺点 其中轻掺杂的下板层位于电容器的介电层下面，并且将这两个辅助重掺杂区域连接到用于电容器的下板的公共电容器电极端子。 如果高电荷施加在覆盖薄介电层的上板上，则辅助P +区容易提供孔。 相反，如果向上板施加高的正电荷，则电子容易由辅助N +区域供应。 通过将辅助N +和P +区域连接在一起，防止施加电压的任一极性的深度耗尽条件。 MOS电容器结构的应用是在绝缘基板上形成的单一事件不安免疫记忆单元中的应用。 具有根据本发明的结构配置的一对MOS电容器耦合在形成存储单元的一对交叉耦合的MOSFET反相器的输入和输出节点之间。

公开(公告)号：US4607316A

公开(公告)日：1986-08-19

申请号：US805094

申请日：1985-12-04

Applicant: Takeshi Wada ,  Hiroshi Kishi ,  Shunji Murai ,  Masami Fukui

Inventor： Takeshi Wada ,  Hiroshi Kishi ,  Shunji Murai ,  Masami Fukui

IPC: C04B35/49 ,  C04B35/46 ,  C04B35/468 ,  H01B3/12 ,  H01G4/12 ,  H01G1/005 ,  H01G4/06

CPC classification number: H01G4/1245 ,  C04B35/4682

Abstract: A monolithic ceramic capacitor having a higher DC breakdown voltage per unit thickness of the dielectric ceramic body than heretofore. The major ingredient of the ceramic is expressed as {(Ba.sub.1-x-y Ca.sub.x Sr.sub.y)O}.sub.k (Ti.sub.1-z Zr.sub.z)O.sub.2, where x, y, z and k are numerals in the ranges specified herein. To this major ingredient is added a minor proportion of a mixture of boric oxide, silicon dioxide, and lithium oxide. The relative proportions of these additives are also specified. For the fabrication of capacitors having dielectric bodies of the above composition, the moldings of the mixture of the major ingredient and additives in the specified proportions are sintered to maturity in a reductive or neutral atmosphere and then reheated at a lower temperature in an oxidative atmosphere. The sintering temperature can be so low (1000.degree.-1200.degree. C.) that the moldings can be cosintered with base metal electrodes buried therein.

Abstract translation: 一种单片陶瓷电容器，其电介质陶瓷体的单位厚度的直流击穿电压高于迄今为止。 陶瓷的主要成分表示为{（Ba1-x-yCaxSry）O} k（Ti1-zZrz）O2，其中x，y，z和k是本文所指定范围内的数字。 向该主要成分添加少量的氧化硼，二氧化硅和氧化锂的混合物。 还规定了这些添加剂的相对比例。 为了制造具有上述组成的电介质体的电容器，将主要成分和特定比例的添加剂的混合物的模制品在还原性或中性气氛中烧结成熟，然后在较低温度下在氧化气氛中再加热。 烧结温度可以如此低（1000°-1200℃），模制品可以与埋在其中的贱金属电极共烧结。

公开(公告)号：US4188651A

公开(公告)日：1980-02-12

申请号：US890343

申请日：1978-03-27

Applicant: John E. Dornfeld ,  Bobby L. Joyner

Inventor： John E. Dornfeld ,  Bobby L. Joyner

IPC: H01G4/12 ,  H01G4/005 ,  H01G4/012 ,  H01G4/28 ,  H01G1/005 ,  H01G4/08

CPC classification number: H01G4/28

Abstract: A reduced barium titanate ceramic capacitor in the form of a rod has closely-spaced electrodes connected in parallel or two spiraled electrodes on the surface thereof and a dielectric layer underneath each. By reducing both the distance between adjacent electrodes and the width of the electrodes, a capacitor with a low power factor is obtained.

Abstract translation: 呈杆形状的还原的钛酸钡陶瓷电容器具有平行连接的紧密间隔的电极或其表面上的两个螺旋形电极和其下方的电介质层。 通过减小相邻电极之间的距离和电极的宽度，获得具有低功率因数的电容器。

公开(公告)号：US4109292A

公开(公告)日：1978-08-22

申请号：US711445

申请日：1976-08-04

Applicant: Masayoshi Shibayama ,  Yuji Nakano ,  Youji Shimizu

Inventor： Masayoshi Shibayama ,  Yuji Nakano ,  Youji Shimizu

IPC: H01G4/12 ,  H01G4/005 ,  H01G4/008 ,  H01G4/28 ,  H01G4/35 ,  H01G13/06 ,  H01G1/005 ,  H01G4/06

CPC classification number: H01G4/008 ,  H01G4/28

Abstract: A tubular ceramic body has formed thereon inner and outer electrodes each comprising a nickel layer in direct contact with the ceramic body and a solder layer overlying the nickel layer. Of tin-lead composition, the solder layer is intended to make leads or the like readily solderable to the electrodes. According to the manufacturing process of the capacitor, the nickel layer is formed by electroless plating, and the solder layer by electroplating.

公开(公告)号：US3989987A

公开(公告)日：1976-11-02

申请号：US598175

申请日：1975-07-23

Applicant: Henricus Hubertus Marie Vorst

Inventor： Henricus Hubertus Marie Vorst

IPC: H01G4/12 ,  H01G20060101 ,  H01G4/005 ,  H01G4/06 ,  H01G4/228 ,  H01R4/02 ,  H01G1/005

CPC classification number: H01G4/228

Abstract: A capacitor which has been given a predetermined capacitance by sand-blasting, in which an additional metal layer of higher conductivity is galvanically deposited over the electrodes, over the junctions of the supply wire and the electrode, and over a portion of the supply wire.

Abstract translation: 通过喷砂给予预定电容的电容器，其中在电极上的电极和电极的接合点之间以及电源线的一部分上方，在电极上电沉积了更高传导性的附加金属层。