公开(公告)号：US09100182B2

公开(公告)日：2015-08-04

申请号：US13358222

申请日：2012-01-25

Applicant: Christian Volf Olgaard ,  Ray Wang

Inventor： Christian Volf Olgaard ,  Ray Wang

IPC: G01R31/00 ,  H04L1/24 ,  H04L1/06 ,  H04B7/04

CPC classification number: H04L1/244 ,  H04B7/0413 ,  H04L1/06 ,  H04L1/243

Abstract: A digital communications test system and method for testing a plurality of devices under test (DUTs) in which multiple sets of a single vector signal analyzer (VSA) and single vector signal generator (VSG) can be used together to perform error vector magnitude (EVM) measurements for one or more DUTs in parallel, including one or more of composite, switched and multiple input multiple output (MIMO) EVM measurements. This allows N pairs of a VSA and VSG to test N DUTs with N×N MIMO in substantially the sane time as a single VSA and VSG pair can test a single DUT, thereby allowing a substantial increase in testing throughput as compared to that possible with only a single VSA and VSG set.

公开(公告)号：US20150185278A1

公开(公告)日：2015-07-02

申请号：US14531612

申请日：2014-11-03

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Ching-Yao Su ,  Liang-Wei Huang ,  Shih-Wei Wang ,  Sheng-Fu Chuang

IPC: G01R31/28

CPC classification number: G01R31/2837 ,  G01R31/2841 ,  H04L1/243

Abstract: The present invention discloses a temperature insensitive testing device comprising: a transmission-end test sequence generating circuit to generate a test sequence; a transmission circuit to process the test sequence according to a transmission clock and thereby generate a test signal; a reception circuit to process an echo of the test signal and generate a digital echo signal; a correlation-value generating circuit to generate correlation values including a maximum correlation value according to the test sequence and the digital echo signal; and a decision circuit to determine whether a relation between the maximum correlation value and at least one threshold satisfies a predetermined condition and thereby generate a decision result, wherein the frequency of the transmission clock is lower than a predetermined frequency which confines the variation of the maximum correlation value to a predetermined range provided that the temperature variation of the transmission cable is within a temperature variation range.

Abstract translation: 本发明公开了一种温度不敏感测试装置，包括：发送端测试序列产生电路，用于产生测试序列; 传输电路，用于根据传输时钟处理测试序列，从而产生测试信号; 接收电路，用于处理测试信号的回波并产生数字回波信号; 相关值产生电路，用于产生包括根据测试序列和数字回声信号的最大相关值的相关值; 以及确定所述最大相关值和至少一个阈值之间的关系是否满足预定条件并由此产生判定结果的判定电路，其中所述传输时钟的频率低于限制所述最大相关值的最大值的变化的预定频率 相关值为预定范围，前提是传输电缆的温度变化在温度变化范围内。

公开(公告)号：US09049020B2

公开(公告)日：2015-06-02

申请号：US12792279

申请日：2010-06-02

Applicant: James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

Inventor： James P. Flynn ,  Junqi Hua ,  John T. Stonick ,  Daniel K. Weinlader ,  Jianping Wen ,  Skye Wolfer ,  David A. Yokoyama-Martin

IPC: G06F1/04 ,  H04L1/24

CPC classification number: H04L1/243

Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.

Abstract translation: 描述了用于简化串行接口测试的电路。 具体地，本发明的一些实施例便于测试接收机的时钟和数据恢复功能。 串行接口可以包括乘法锁相环（MPLL）时钟发生器，发射器和接收器。 MPLL时钟发​​生器可以产生第一时钟信号和第二时钟信号，并且可以改变第一时钟信号和第二时钟信号之间的相位和/或频率差。 在测试期间，发射机和接收机可以彼此直接或电容耦合。 具体来说，在测试期间，串行接口可被配置为使发射机使用第一时钟信号发射数据，并且接收机使用第二时钟信号接收数据。 接收机的时钟和数据恢复功能可以通过比较发送的数据与接收到的数据进行测试。

公开(公告)号：US08810072B2

公开(公告)日：2014-08-19

申请号：US13154965

申请日：2011-06-07

Applicant: Ming-Chiu Tsai ,  Chi-Che Chan

Inventor： Ming-Chiu Tsai ,  Chi-Che Chan

IPC: H01F38/14 ,  H02J7/02 ,  H02J5/00

CPC classification number: H02J50/80 ,  H02J5/005 ,  H02J7/025 ,  H02J50/12 ,  H02J50/70 ,  H04L1/243

Abstract: A high-power induction-type power supply system includes a supplying-end module consisting of a supplying-end microprocessor, a power driver unit, a signal analysis circuit, a coil voltage detection circuit, a display unit, a power supplying unit, a resonant circuit and a supplying-end coil, and a receiving-end module consisting of a receiving-end microprocessor, a voltage detection circuit, a rectifier and filter circuit, an amplitude modulation circuit, a protection circuit breaker, a voltage stabilizer circuit, a DC-DC buck converter, a resonant circuit and a receiving-end coil. By means of single bit data analysis to start up power supply, sensing signal transmitting time during standby mode is minimized. Subject to asymmetric data signal data encoding and decoding system to recognize data code, power loss is minimized during synchronous transmission of power supply and data signal, and a high capacity of fault tolerance is achieved.

Abstract translation: 一种高功率感应型电源系统，包括：供电端模块，由供电端微处理器，功率驱动单元，信号分析电路，线圈电压检测电路，显示单元，供电单元， 谐振电路和供电端线圈，以及由接收端微处理器，电压检测电路，整流器和滤波电路组成的接收端模块，振幅调制电路，保护断路器，稳压电路， DC-DC降压转换器，谐振电路和接收端线圈。 通过单位数据分析启动电源，待机模式下的感应信号传输时间最小化。 受非对称数据信号数据编码和解码系统识别数据码的影响，在电源和数据信号的同步传输过程中功率损耗最小化，实现了高容量容错。

公开(公告)号：US20140226511A1

公开(公告)日：2014-08-14

申请号：US14172670

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Maxim Gotman

IPC: H04B17/00 ,  H04W72/04

CPC classification number: H04W72/042 ,  H04B7/0417 ,  H04B17/11 ,  H04B17/12 ,  H04B17/14 ,  H04B17/24 ,  H04L1/0026 ,  H04L1/06 ,  H04L1/1867 ,  H04L1/20 ,  H04L1/243 ,  H04W52/08

Abstract: Methods, systems, and devices are described for calibrating a transmit path of a base station. A calibration symbol of a subframe may be generated for transmission on a downlink channel. The calibration symbol of the subframe may be transmitted. The calibration symbol may include a predefined waveform to calibrate the transmit path of the base station. At least part of the subframe including the calibration symbol may be received through a dedicated feedback receive path. The transmit path may be calibrated based at least in part on the received calibration symbol. The calibration symbols may replace one or more data symbols of the subframe. Control symbols may also be transmitted during the subframe. The control symbols may include reference signals and downlink control channels. The control symbols may signal to a mobile device a zero allocation of downlink resources during the subframe.

Abstract translation: 描述了用于校准基站的发射路径的方法，系统和设备。 可以生成子帧的校准符号用于在下行链路信道上进行传输。 可以发送子帧的校准符号。 校准符号可以包括用于校准基站的发射路径的预定波形。 可以通过专用反馈接收路径来接收包括校准符号的子帧的至少一部分。 可以至少部分地基于所接收的校准符号来校准发送路径。 校准符号可以替代子帧的一个或多个数据符号。 也可以在子帧期间发送控制符号。 控制符号可以包括参考信号和下行链路控制信道。 在子帧期间，控制符号可以向移动设备发送下行链路资源的零分配。

公开(公告)号：US08780737B2

公开(公告)日：2014-07-15

申请号：US13333656

申请日：2011-12-21

Applicant: Seung-Kwon Cho ,  Hun-Sik Kang ,  Sok-Kyu Lee

Inventor： Seung-Kwon Cho ,  Hun-Sik Kang ,  Sok-Kyu Lee

IPC: H04L12/26 ,  H04W74/08 ,  G06F11/07

CPC classification number: H04W74/0808 ,  G06F11/0751 ,  H04L1/243

Abstract: Disclosed is a loop-back apparatus in wireless communication systems, including: an MAC processing unit configured to transmit a user data and a control frame when a loop-back mode is established; a loop-back unit configured to generate a response frame of a receipt for the user data and the control message transmitted from the MAC processing unit and again feedbacks the generated response frame to the MAC processing unit.

Abstract translation: 公开了一种无线通信系统中的环回装置，包括：MAC处理单元，被配置为在建立环回模式时发送用户数据和控制帧; 循环单元，被配置为生成用于所述用户数据的接收的响应帧和从所述MAC处理单元发送的所述控制消息，并且将所生成的响应帧再次反馈给所述MAC处理单元。

公开(公告)号：US20140161167A1

公开(公告)日：2014-06-12

申请号：US14172214

申请日：2014-02-04

Applicant: AWARE, INC.

Inventor： Ling Zheng ,  Michael A. Lund

IPC: H04B3/46

CPC classification number: H04B3/46 ,  H04B3/48 ,  H04L1/243

Abstract: Prediction of a channel capacity is accomplished based on a TDR echo without explicitly estimating the topology of the line. The prediction is based on obtaining a measured TDR echo, determining a theoretical TDR echo for a plurality of loop lengths, estimating the equivalent TDR length based on an optimization, updating the equivalent TDR length and utilizing the updated TDR length to predict one or more of the upstream and downstream data rates.

Abstract translation: 信道容量的预测是基于TDR回波完成的，而不明确地估计线路的拓扑。 该预测基于获得测量的TDR回波，确定多个环路长度的理论TDR回波，基于优化估计等效TDR长度，更新等效TDR长度并利用更新的TDR长度预测一个或多个 上下游数据速率。

公开(公告)号：US08724483B2

公开(公告)日：2014-05-13

申请号：US11977092

申请日：2007-10-22

Applicant: Ting Sheng Ku ,  Russell Newcomb ,  Barry A. Wagner ,  Ashfaq R. Shaikh ,  William B. Simms

Inventor： Ting Sheng Ku ,  Russell Newcomb ,  Barry A. Wagner ,  Ashfaq R. Shaikh ,  William B. Simms

IPC: G06F11/00

CPC classification number: G01R31/31716 ,  H04L1/243

Abstract: An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Abstract translation: 公开了一种用于实现提供改进的电子系统的校准和/或测试的环回配置的接口。 更具体地，实施例提供具有能够相反方向传送数据的至少两个部分或分区的双向接口，并且在电子系统的组件之间实现环回配置，从而实现更灵活，有效和有效的校准和/或测试 电子系统使用单一接口。 分区双向接口的环回可用于执行数据链路训练和/或电子系统测试。 在一个实施例中，接口的环回配置可以是可逆的。 此外，分区的环路或耦合端可以从一个组件切换到另一个组件，从而在一个实施例中反转环回的配置。 因此，与常规环回配置相比，实施例使得能够执行不同的和/或附加的校准操作和/或测试。

公开(公告)号：US08711711B2

公开(公告)日：2014-04-29

申请号：US13089906

申请日：2011-04-19

Applicant: Charles J. Kim

Inventor： Charles J. Kim

IPC: H04L12/26

CPC classification number: G01R31/02 ,  H04B10/0771 ,  H04L1/243 ,  H04L25/0266 ,  H04L25/0268 ,  H04L27/02 ,  H04L27/10 ,  H04L27/18 ,  H04L41/0677 ,  H04L2001/0094 ,  Y04S40/166

Abstract: Data associated with at least one building condition or status is sensed by one or more sensors. The data from these sensors may be sent over a data bus and received by the central computer. In addition, a modulated signal may be transmitted by one or both of the transmitters across the data bus. The modulated signal is received at the receiver, which analyzes the received modulated signal, and determines whether an intermittent fault has occurred on the data bus based upon the analyzing. For example, the receiver may compare the received signal to an expected pattern and when a discrepancy exists, an intermittent fault is determined to exist. The receiver may also determine the location of the fault based upon the analysis.

Abstract translation: 与至少一个建筑物状况或状态相关联的数据由一个或多个传感器感测。 来自这些传感器的数据可以通过数据总线发送并由中央计算机接收。 此外，调制信号可以由数据总线中的一个或两个发射器发送。 在接收机处接收调制信号，该接收机分析接收到的调制信号，并基于分析确定数据总线上是否发生了间歇故障。 例如，接收机可以将接收到的信号与预期模式进行比较，并且当存在差异时，确定存在间歇性故障。 接收机还可以基于分析来确定故障的位置。

公开(公告)号：US20130244584A1

公开(公告)日：2013-09-19

申请号：US13848749

申请日：2013-03-22

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)

Inventor： Leif Mattison ,  Béla Rathonyi

IPC: H04W24/06

CPC classification number: H04W24/06 ,  H04L1/243 ,  H04L41/0866 ,  H04L41/12 ,  H04L43/50 ,  H04W36/00 ,  H04W36/0005 ,  H04W76/19 ,  H04W76/30

Abstract: A method for verifying compliance of a communication device with one or more requirement specifications is disclosed. The method comprises establishing a link between a test system and the communication device, wherein the establishing comprises configuring one or more bearers and one or more control channels; closing a test loop comprising the test system and the communication device, wherein the closing comprises activating a test loop function of the communication device; sending data in a downlink of the test loop from the test system to the communication device; receiving the data at the communication device; transferring at least some of the data to an uplink transmission arrangement of the communication device after a specific event has occurred; and verifying, at the test system, transmission in an uplink of the test loop from the communication device to the test system. Corresponding test system and test loop function arrangement are also disclosed.

Abstract translation: 公开了一种用于验证通信设备与一个或多个要求规范的符合性的方法。 该方法包括建立测试系统和通信设备之间的链路，其中建立包括配置一个或多个承载和一个或多个控制信道; 关闭包括所述测试系统和所述通信设备的测试回路，其中所述关闭包括激活所述通信设备的测试循环功能; 将测试循环的下行链路中的数据从测试系统发送到通信设备; 在通信设备处接收数据; 在特定事件发生之后将至少一些数据传送到通信设备的上行链路传输布置; 以及在所述测试系统处验证所述测试环路的上行链路中的从所述通信设备到所述测试系统的传输。 还公开了相应的测试系统和测试环路功能布置。