Transpose memory for DCT/IDCT circuit
    12.
    发明授权
    Transpose memory for DCT/IDCT circuit 失效
    用于DCT / IDCT电路的转置存储器

    公开(公告)号:US5481487A

    公开(公告)日:1996-01-02

    申请号:US189446

    申请日:1994-01-28

    CPC classification number: G11C8/12 G06F17/147 G06F9/30141 G06T9/007

    Abstract: A transpose memory is disclosed which has four dual port memories, a first counter for writing elements in the dual port memories and a second counter for reading out elements from the dual port memories. If the received matrix is to be outputted to the first type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the quadrant of the matrix element. If the received matrix is to be outputted to the second type of transform circuit, the first counter writes each matrix element in a particular dual port memory assigned to the "evenness" or "oddness" (i.e., divisibleness by two) of the row and column of the matrix element.

    Abstract translation: 公开了一种转置存储器,其具有四个双端口存储器,用于在双端口存储器中写入元件的第一计数器和用于从双端口存储器读出元件的第二计数器。 如果接收的矩阵要输出到第一类型的变换电路,则第一计数器将每个矩阵元素写入分配给矩阵元素的象限的特定双端口存储器中。 如果接收的矩阵要被输出到第二类型的变换电路,则第一个计数器将每个矩阵元素写入分配给该行的“均匀度”或“奇数”(即,二分之二)的特定双端口存储器中, 矩阵元素的列。

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