公开(公告)号：US20210258284A1

公开(公告)日：2021-08-19

申请号：US17246310

申请日：2021-04-30

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US11012411B2

公开(公告)日：2021-05-18

申请号：US16180883

申请日：2018-11-05

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Neil Turton ,  David James Riddoch ,  Dmitri Kitariev ,  Ripduman Sohan ,  Derek Edward Roberts

IPC: H04L29/06

Abstract: A network interface device having a hardware module comprising a plurality of processing units. Each of the plurality of processing units is associated with its own at least one predefined operation. At a compile time, the hardware module is configured by arranging at least some of the plurality of processing units to perform their respective at least one operation with respect to a data packet in a certain order so as to perform a function with respect to that data packet. A compiler is provide to assign different processing stages to each processing unit. A controller is provided to switch between different processing circuitry on the fly so that one processing circuitry may be used whilst another is being compiled.

公开(公告)号：US20250147799A1

公开(公告)日：2025-05-08

申请号：US18501868

申请日：2023-11-03

Applicant: Xilinx, Inc.

Inventor： Thomas Calvert ,  Ripduman Sohan ,  Dmitri Kitariev ,  Kimon Karras ,  Stephan Diestelhorst ,  Neil Turton ,  David Riddoch ,  Derek Roberts ,  Kieran Mansley ,  Steven Pope

IPC: G06F9/48

Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.

公开(公告)号：US11960596B2

公开(公告)日：2024-04-16

申请号：US17199200

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F21/53 ,  G06F21/57 ,  H04L9/40

CPC classification number: G06F21/53 ,  G06F21/57 ,  H04L63/0218

Abstract: A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.

公开(公告)号：US11165720B2

公开(公告)日：2021-11-02

申请号：US15847742

申请日：2017-12-19

Applicant: XILINX, INC.

Inventor： Steven L. Pope ,  Dmitri Kitariev ,  Derek Roberts

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/707 ,  H04L12/801 ,  G06N20/00 ,  G06F9/50 ,  G06F30/394

Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.

公开(公告)号：US20210255987A1

公开(公告)日：2021-08-19

申请号：US17308871

申请日：2021-05-05

Applicant: Xilinx, Inc.

Inventor： Steven L. Pope ,  David J. Riddoch ,  Dmitri Kitariev

IPC: G06F15/173 ,  H04L12/26 ,  G06F13/38

Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.

公开(公告)号：US20250004941A1

公开(公告)日：2025-01-02

申请号：US18346017

申请日：2023-06-30

Applicant: Xilinx, Inc.

Inventor： Duncan Andrew Cockburn ,  David James Fraser ,  Inaki Ormaetxea ,  Gareth David Edwards ,  Dmitri Kitariev ,  David Riddoch ,  Victor Wu

IPC: G06F12/02

Abstract: A computer-implemented method for memory management can include identifying a set of one or more memory blocks of virtual memory to be allocated for storage of a content into a plurality of memory banks that subdivide physical memory. The method can include storing the content in the set of one or more memory blocks of virtual memory. The method can include assigning an identifier to the set of one or more memory blocks of virtual memory that store the content. The method can include outputting the identifier for the set of one or more memory blocks of virtual memory. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11966351B2

公开(公告)日：2024-04-23

申请号：US17199197

申请日：2021-03-11

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F9/445 ,  G06F9/48 ,  G06F11/36 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F9/4881

Abstract: A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.

公开(公告)号：US11726928B2

公开(公告)日：2023-08-15

申请号：US17357083

申请日：2021-06-24

Applicant: XILINX, INC.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  Dmitri Kitariev ,  Neil Duncan Turton ,  David James Riddoch ,  Ripduman Sohan

IPC: G06F13/16 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F13/1621 ,  G06F13/1642 ,  G06F13/1678 ,  G06F13/287 ,  G11C7/1069 ,  G11C7/1096

Abstract: A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

公开(公告)号：US20230006945A1

公开(公告)日：2023-01-05

申请号：US17867646

申请日：2022-07-18

Applicant: Xilinx, Inc.

Inventor： Steven L. Pope ,  Derek Roberts ,  David J. Riddoch ,  Dmitri Kitariev

IPC: H04L49/506 ,  H04L49/90 ,  H04L49/00 ,  H04L69/16 ,  H04L49/103 ,  H04L45/00 ,  H04L49/101

Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.