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公开(公告)号：US11741872B2
公开(公告)日：2023-08-29
申请号：US17046835
申请日：2020-06-23
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2300/0408 , G09G2300/0426 , G09G2310/0267 , G09G2310/08
Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a first pull-down module for pulling down a voltage level of a current-stage gate driving signal, a second pull-down module for pulling down a voltage level of the first node, a third pull-down module for pulling down a voltage level of the second node, and a fourth pull-down module for pulling down the voltage level of the current-stage gate driving signal. The GOA circuit raises the effect of pulling down the current-stage gate driving signal.
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Patent Agency Ranking
公开(公告)号：US11682330B2
公开(公告)日：2023-06-20
申请号：US16970649
申请日：2020-06-24
Inventor： Jian Tao
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2300/0408 , G09G2310/08
Abstract: In a GOA circuit and a display panel provided by embodiments of the present application, a reset module is provided in each level of GOA units, so that each level of the GOA units can output a high potential before an end of a frame, all gates in a display area are turned on, and a charge of all pixels in the display area is discharged; after that, each level of the GOA units outputs a low potential, and all of the gates in the display area are set to the low potential.
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13.发明授权公开(公告)号：US11322108B2
公开(公告)日：2022-05-03
申请号：US16766748
申请日：2020-03-17
Inventor： Jian Tao
IPC: G09G3/36
Abstract: A gate driver of array (GOA) circuit includes a plurality of cascaded GOA units, wherein an N-th GOA unit includes a scan control circuit, a reverse circuit, a gate signal output circuit, and a potential holding circuit. The reverse circuit is coupled to the scan control circuit. The gate signal output circuit is coupled to an Nth clock signal, the scan control circuit, and the reverse circuit. The potential holding circuit is coupled to the scan control circuit, the reverse circuit, and the gate signal output circuit.
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公开(公告)号：US11315512B2
公开(公告)日：2022-04-26
申请号：US16652167
申请日：2020-03-24
Abstract: A gate driver on array (GOA) circuit is provided. The GOA circuit includes a plurality of cascading GOA units. One of the GOA unit includes: a scan control module, an anti-backfill module connected to a constant high-level signal and the scan control module, a cascading reset module, and a gate signal output module. Base on functions of prior art solution, the provided GOA circuit of the disclosure reduces two types of signal to simplify signal traces at the bezel to realize a narrow bezel design.
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公开(公告)号：US11275282B2
公开(公告)日：2022-03-15
申请号：US16764419
申请日：2020-01-09
IPC: G02F1/1362 , G02F1/1335 , G02F1/1343 , G09G3/36 , G02F1/133 , G02F1/1333 , G09G3/00 , G02F1/1345
Abstract: The present application provides a liquid crystal display panel and a display device. Invalid pixels of the liquid crystal display panel include a test pixel. In this structure, when no tests are required, the test pixel is in an off state, and there is no voltage difference between a pixel electrode and a common electrode to cause rotation of liquid crystals. When a test is required, the test pixel is in an on state, and the pixel electrode is disconnected from the common electrode to cause a voltage difference, so that the liquid crystals are normally rotated.
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公开(公告)号：US20210407451A1
公开(公告)日：2021-12-30
申请号：US16652167
申请日：2020-03-24
IPC: G09G3/36
Abstract: A gate driver on array (GOA) circuit is provided. The GOA circuit includes a plurality of cascading GOA units. One of the GOA unit includes: a scan control module, an anti-backfill module connected to a constant high-level signal and the scan control module, a cascading reset module, and a gate signal output module. Base on functions of prior art solution, the provided GOA circuit of the disclosure reduces two types of signal to simplify signal traces at the bezel to realize a narrow bezel design.
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