公开(公告)号：US20220157690A1

公开(公告)日：2022-05-19

申请号：US17097441

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC: H01L23/373 ,  H01L23/48 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20210193505A1

公开(公告)日：2021-06-24

申请号：US16876432

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC: H01L21/768 ,  H01L23/532

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.

公开(公告)号：US20210376111A1

公开(公告)日：2021-12-02

申请号：US16888138

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.