公开(公告)号：US10269907B2

公开(公告)日：2019-04-23

申请号：US15918394

申请日：2018-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Chih-Hao Chang ,  Sheng-Yu Chang ,  Jen-Hsiang Lu ,  Jyun-Yang Shen

IPC: H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.

公开(公告)号：US20180138280A1

公开(公告)日：2018-05-17

申请号：US15353922

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Li ,  Jen-Hsiang LU ,  Chih-Hao CHANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L23/522 ,  H01L21/28 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate, at least one gate stack, a gate spacer and a dielectric cap. The gate stack is located on the semiconductor substrate. The gate spacer is located on a sidewall of the gate stack. The gate spacer includes a first dielectric layer and a second dielectric layer with different etch properties. The dielectric cap at least caps the gate spacer. The dielectric cap and the second dielectric layer define a gap therebetween.