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    Semiconductor Package and Method
    12.
    发明申请
    Semiconductor Package and Method 有权

    公开(公告)号：US20230069031A1

    公开(公告)日：2023-03-02

    申请号：US17412966

    申请日：2021-08-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

    Abstract: A semiconductor structure includes a first redistribution structure, a first local interconnect component disposed on the first redistribution structure, and a first interconnect structure over a second side of the first local interconnect component. The first local interconnect component includes a first plurality of redistribution layers. The first plurality of redistribution layers includes a first plurality of conductive features on a first side of the first local interconnect component. Each of the first plurality of conductive features are coupled to respective conductive features of the first redistribution structure. The first interconnect structure includes a second plurality of conductive features and a third plurality of conductive features. The second plurality of conductive features are electrically coupled to the third plurality of conductive features through the first local interconnect component.

    Semiconductor package and method
    13.
    发明授权
    Semiconductor package and method 有权

    公开(公告)号：US11594498B2

    公开(公告)日：2023-02-28

    申请号：US16931992

    申请日：2020-07-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

    IPC: H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

    Abstract: In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

    Method for manufacturing semiconductor package with connection structures including via groups
    16.
    发明授权
    Method for manufacturing semiconductor package with connection structures including via groups 有权

    公开(公告)号：US11532587B2

    公开(公告)日：2022-12-20

    申请号：US17170268

    申请日：2021-02-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Hsun Chen ,  Jiun Yi Wu ,  Chien-Hsun Lee ,  Chung-Shi Liu

    IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56

    Abstract: A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.

    Via structure for packaging and a method of forming
    19.
    发明授权
    Via structure for packaging and a method of forming 有权

    公开(公告)号：US11410953B2

    公开(公告)日：2022-08-09

    申请号：US16983282

    申请日：2020-08-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Che Ho ,  Yi-Wen Wu ,  Chien Ling Hwang ,  Hung-Jui Kuo ,  Chung-Shi Liu

    IPC: H01L21/56 ,  H01L27/112 ,  H01L23/31 ,  H01L21/48 ,  H01L21/3105 ,  H01L25/065 ,  H01L27/02 ,  H01L23/00

    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

    SEMICONDUCTOR PACKAGE AND METHOD
    20.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD 有权

    公开(公告)号：US20220199461A1

    公开(公告)日：2022-06-23

    申请号：US17205383

    申请日：2021-03-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chen-Hua Yu ,  Wei-Yu Chen ,  Jiun Yi Wu ,  Chung-Shi Liu ,  Chien-Hsun Lee

    IPC: H01L21/768 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

    Abstract: A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.

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