公开(公告)号：US20200185499A1

公开(公告)日：2020-06-11

申请号：US16216874

申请日：2018-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

公开(公告)号：US20200161461A1

公开(公告)日：2020-05-21

申请号：US16194794

申请日：2018-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup LEE ,  Jungwoo JOH ,  Pinghai HAO ,  Sameer PENDHARKAR

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20150060949A1

公开(公告)日：2015-03-05

申请号：US14537455

申请日：2014-11-10

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood HAIDER ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/51 ,  H01L29/20 ,  H01L29/49

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。