公开(公告)号：US10211278B2

公开(公告)日：2019-02-19

申请号：US15646917

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.

公开(公告)号：US20210343642A1

公开(公告)日：2021-11-04

申请号：US17378203

申请日：2021-07-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10741473B2

公开(公告)日：2020-08-11

申请号：US16654900

申请日：2019-10-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Archana Venugopal

IPC: H01L49/02 ,  H01L23/42 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485

Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.

公开(公告)号：US10680056B1

公开(公告)日：2020-06-09

申请号：US16232653

申请日：2018-12-26

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Brian Goodlin ,  Dhishan Kande

IPC: H01L21/00 ,  H01L49/02 ,  H01L21/70 ,  H01L21/66 ,  H01C17/24 ,  H01L21/822 ,  H01C7/00

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.

公开(公告)号：US20200051893A1

公开(公告)日：2020-02-13

申请号：US16654900

申请日：2019-10-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Archana Venugopal

IPC: H01L23/42 ,  H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485

Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.

公开(公告)号：US10439020B2

公开(公告)日：2019-10-08

申请号：US15855635

申请日：2017-12-27

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Shih Chang Chang

IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/01

Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.

公开(公告)号：US20190295948A1

公开(公告)日：2019-09-26

申请号：US16423723

申请日：2019-05-28

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.