公开(公告)号：US20240237564A1

公开(公告)日：2024-07-11

申请号：US18236651

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sukhwan CHUNG ,  Zhe WU ,  Jung Moo LEE ,  Hideki HORII

IPC: H10N70/00 ,  C22C30/00 ,  H10B63/00 ,  H10B63/10 ,  H10N70/20

CPC classification number: H10N70/8828 ,  C22C30/00 ,  H10B63/10 ,  H10B63/24 ,  H10N70/231

Abstract: A variable resistance memory device includes a first electrode; a variable resistance material on the first electrode; and a second electrode on the variable resistance material, wherein the variable resistance material includes an impurity (A) and is represented as ApGexSbyTez, an atomic concentration ‘x’ of the germanium is 0.4≤x≤0.5, an atomic concentration ‘z’ of the tellurium is 0.3≤z

公开(公告)号：US20240177771A1

公开(公告)日：2024-05-30

申请号：US18334790

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soyeon CHOI ,  Zhe WU ,  Chungman KIM ,  Seunggeun YU ,  Jabin LEE

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/004

Abstract: An operating method of a self-selecting memory device, includes an operation of applying a first write pulse corresponding to a first state to a first memory cell during a first pulse width, and an operation of applying a second write pulse corresponding to a second state to a second memory cell during a second pulse width, wherein the first write pulse and the second write pulse have substantially opposite polarities, wherein the first pulse width is longer than the second pulse width.

公开(公告)号：US20210313397A1

公开(公告)日：2021-10-07

申请号：US17019649

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Kwangmin PARK ,  Zhe WU

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.

公开(公告)号：US20200091234A1

公开(公告)日：2020-03-19

申请号：US16386893

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo LEE ,  Zhe WU ,  Kyubong JUNG ,  Seung-geun YU ,  Ja Bin LEE

IPC: H01L27/24 ,  H01L45/00

Abstract: A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.