公开(公告)号：US10950619B2

公开(公告)日：2021-03-16

申请号：US16223894

申请日：2018-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  Sunghan Cho

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

公开(公告)号：US10818687B2

公开(公告)日：2020-10-27

申请号：US15991476

申请日：2018-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Young-Jin Jung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11575 ,  H01L27/11548 ,  H01L27/11573 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.