公开(公告)号：US11335689B2

公开(公告)日：2022-05-17

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US11037991B2

公开(公告)日：2021-06-15

申请号：US16392099

申请日：2019-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo Kang ,  Changwoo Seo ,  Dain Lee ,  Wook-Yeol Yi ,  Hoi Sung Chung

IPC: H01L45/02 ,  H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.

公开(公告)号：US08853660B2

公开(公告)日：2014-10-07

申请号：US13668489

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： JaeJong Han ,  Sungun Kwon ,  Jinhye Bae ,  Kongsoo Lee ,  Seong Hoon Jeong ,  Yoongoo Kang ,  Ho-Kyun An

IPC: H01L29/02

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/141

Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Abstract translation: 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。