公开(公告)号：US20220027090A1

公开(公告)日：2022-01-27

申请号：US17154030

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F3/06 ,  G06F1/08

Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

公开(公告)号：US10911378B2

公开(公告)日：2021-02-02

申请号：US16270954

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungjin Kim ,  Yongsuk Kwon ,  Myeongcheol Kim ,  Yoonsung Nam ,  Hyongjin Ban ,  Sangsoo Lee

IPC: G06F15/16 ,  H04L12/58

Abstract: An electronic device may be configured to receive a message for a second external electronic device, from a first external electronic device through a first network associated with the first external electronic device among a plurality of rich communication suite (RCS) networks using a communication circuit, to determine whether to transmit the message based on a profile of the second external electronic device including at least one throttling metric for the first network among the plurality of RCS networks stored in a memory and a network state of the first network, and to convert the message based on a protocol of a second network and to transmit the converted message to the second external electronic device through the second network based on determining to transmit the message.

公开(公告)号：US12236099B2

公开(公告)日：2025-02-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F12/00 ,  G06F3/06

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240281402A1

公开(公告)日：2024-08-22

申请号：US18460954

申请日：2023-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Jung ,  Younghyun Lee ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jinin So

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/0002

Abstract: A computing system includes an interconnect device, a plurality of memory devices electrically coupled to communicate with the interconnect device, a plurality of host devices electrically coupled to communicate with the interconnect device and configured to generate requests for access to the plurality of memory devices via the interconnect device, and a plurality of congestion monitors. These congestion monitors are configured to generate congestion information by monitoring a congestion degree of signal transfers with respect to at least one of the plurality of memory devices and the interconnect device in real time. The computing system is also configured to control at least one of: a memory region allocation of the plurality of host devices to the plurality of memory devices, and a signal transfer path inside the interconnect device, based on the congestion information.

公开(公告)号：US20240248609A1

公开(公告)日：2024-07-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240201858A1

公开(公告)日：2024-06-20

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US11531618B2

公开(公告)日：2022-12-20

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4093 ,  G11C11/4096 ,  H04N21/426

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

公开(公告)号：US20210390049A1

公开(公告)日：2021-12-16

申请号：US17157323

申请日：2021-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4096 ,  G11C11/4093

Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.