公开(公告)号：US20200228211A1

公开(公告)日：2020-07-16

申请号：US16641207

申请日：2017-12-15

Applicant: Samsung Electronics Co., Ltd

Inventor： Manh-Tuan DAO ,  Yonghoon KIM ,  Yuichi AOKI

IPC: H04B17/12 ,  H04B17/10 ,  H04B7/06

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as long-term evolution (LTE). The present disclosure provides a device and a method for calibrating a phased array antenna. A method for calibrating a phased array antenna according to various embodiments of the disclosure comprises the processes of: controlling a first radio frequency (RF) chain so as to transmit a first signal at a first phase, thereby determining the phase difference between the first phase and a reference phase; controlling the first RF chain so as to transmit a second signal at a second phase, thereby determining the phase condition of the phase difference; and calibrating the first RF chain on the basis of the phase difference and the phase condition. The reference phase may be the phase of a reference signal transmitted from a reference RF chain. Accordingly, the time necessary for calibration may be reduced, and mass production of phased array antennas may be facilitated. The present research has been financed by the Korean government (Ministry of Science and ICT) in 2017 and conducted with the support of “Intra-ministry Giga Korean Project” (No. GK17N0100, Millimeter-wave 5G Mobile Communication System Development).

公开(公告)号：US20190244945A1

公开(公告)日：2019-08-08

申请号：US16201361

申请日：2018-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon KIM

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a logic chip on the package substrate, a memory stack structure on the package substrate and including first and second semiconductor chips stacked along a first direction, and a first bump between the package substrate and the memory stack structure. The logic chip and the memory stack are spaced apart along a second direction, crossing the first direction, on the package substrate. The first semiconductor chip includes a through via electrically connected to the second semiconductor chip, a chip signal pad connected to the through via, and a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad in contact with the first bump. A distance between the logic chip and the edge signal pad along the second direction is less than that between the logic chip and the chip signal pad.

公开(公告)号：US20230378985A1

公开(公告)日：2023-11-23

申请号：US18230899

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichi AOKI ,  Heedo KANG ,  Yonghoon KIM ,  Wonki KIM

IPC: H04B1/04 ,  H04B1/00

CPC classification number: H04B1/0475 ,  H04B1/0028 ,  H04B2001/0425

Abstract: A communication device includes a transmitter that, in a first operation, distorts an input signal through a digital predistortion unit, converts the distorted input signal into an analog signal, performs frequency up-conversion on the converted analog signal to generate a first signal, amplifies the generated first signal through a power amplifier, and couples the amplified first signal; a receiver that, in the first operation, receives the coupled first signal from the transmitter, performs frequency down-conversion on the coupled first signal so as to generate a second signal, and converts the generated second signal into a digital signal through one or more analog-to-digital converters that are turned on, among a plurality of analog-to-digital converters; and a processor that, in the first operation, causes one or more of the plurality of analog-to-digital converters to be turned on and a remainder of the plurality of analog-to-digital converters to be turned off.

公开(公告)号：US20230299480A1

公开(公告)日：2023-09-21

申请号：US18202163

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihyun KIM ,  Seokhyeon KIM ,  Yonghoon KIM ,  Hyunchul PARK

IPC: H01Q3/44 ,  H01Q9/28

CPC classification number: H01Q3/443 ,  H01Q9/28

Abstract: In a 5th generation (5G) or pre-5G communication system for supporting a high data transfer rate, a method of measuring a power of a signal in an electronic device may include obtaining, by at least one sensor, a first voltage of the signal at a first point between a power amplifier and a transmission line, obtaining, by the at least one sensor, a second voltage of the signal at a second point between the transmission line and an antenna, and calculating a power of the signal, based on the first voltage and the second voltage. A length of the transmission line may be based on a wavelength of the signal. The method and corresponding electronic device reduce an error between power to be calculated and power consumed in practice.

公开(公告)号：US20230031668A1

公开(公告)日：2023-02-02

申请号：US17758494

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichi AOKI ,  Tuan Manh DAO ,  Daehyun KANG ,  Yonghoon KIM ,  Yongan HWANG

IPC: H01Q3/26 ,  H01Q3/30

Abstract: The present disclosure relates to a communication technique for merging, with an IoT technology, a 5G communication system for supporting a higher data transmission rate than a 4G system, and a system therefor. The present disclosure can be applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security- and safety-related services, and the like) on the basis of a 5G communication technology and an IoT-related technology. The present disclosure discloses a method for calibration of a phased array antenna.

公开(公告)号：US20210159183A1

公开(公告)日：2021-05-27

申请号：US17165246

申请日：2021-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200335469A1

公开(公告)日：2020-10-22

申请号：US16822300

申请日：2020-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoon KIM ,  Jaehyun LIM ,  Yuntae LEE ,  Sayoon KANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: Provided is a semiconductor package including a package structure including a base connection member including a redistribution layer, a first semiconductor chip including a plurality of first connection pads connected to the redistribution layer, an encapsulant disposed on the base connection member and covering at least a portion of the first semiconductor chip, and a backside connection member disposed on the encapsulant and including a backside wiring layer electrically connected to the redistribution layer, and a second semiconductor chip disposed on the base connection member or the backside connection member, the second semiconductor chip including a plurality of second connection pads connected to the redistribution layer or the backside wiring layer, the second semiconductor chip including a logic circuit, the first semiconductor chip including a logic input and output terminals that are connected to the logic circuit through at least one of the redistribution layer and the backside wiring layer.

公开(公告)号：US20200035611A1

公开(公告)日：2020-01-30

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20160133542A1

公开(公告)日：2016-05-12

申请号：US14825831

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yong CHA ,  Keung Beum KIM ,  Yonghoon KIM ,  HyunJong MOON ,  Heeseok LEE

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1713 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Abstract translation: 半导体封装包括：封装基板，包括第一区域，穿透第一区域并在封装基板的顶表面和底表面处露出的热块;封装基板上的半导体芯片;设置在封装基板和半导体芯片之间的凸块;以及 包括与热块接触的第一凸起，以及设置在封装基板的底表面上并包括与热块接触的第一端子的端子。 热块是功率路径和接地路径之一。