公开(公告)号：US20220285208A1

公开(公告)日：2022-09-08

申请号：US17453504

申请日：2021-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byungkyu KIM ,  Eunji KIM ,  Seungwoo PAEK ,  Sungdong CHO

IPC: H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor chip structure includes a first semiconductor chip that includes a first chip region and a first scribe lane region and a second semiconductor chip that includes a second chip region and a second scribe lane region respectively bonded to the first chip region and the first scribe lane region. The first semiconductor chip includes a first bonding wiring layer that includes a first bonding insulating layer and a first bonding electrode in the first bonding insulating layer. The second semiconductor chip includes a second bonding wiring layer that includes a second bonding insulating layer and a second bonding electrode in the second bonding insulating layer and a polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer.

公开(公告)号：US20250096141A1

公开(公告)日：2025-03-20

申请号：US18961767

申请日：2024-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyeok SON ,  Junwoo LEE ,  Sungdong CHO

IPC: H01L23/535 ,  H01L21/768 ,  H10B12/00

Abstract: A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.

公开(公告)号：US20230178434A1

公开(公告)日：2023-06-08

申请号：US17879049

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyoung KWON ,  Kwangwuk PARK ,  Youngmin LEE ,  Inyoung LEE ,  Sungdong CHO

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L21/76816 ,  H01L23/5283 ,  H01L21/76897

Abstract: A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.

公开(公告)号：US20220336365A1

公开(公告)日：2022-10-20

申请号：US17509463

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dayoung LEE ,  Jun-Woo LEE ,  Sungdong CHO

IPC: H01L23/532 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

公开(公告)号：US20220336327A1

公开(公告)日：2022-10-20

申请号：US17808533

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNJI KIM ,  Sungdong CHO ,  Kwangwuk PARK ,  Sangjun PARK ,  Daesuk LEE ,  Hakseung LEE

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate having an active surface on which semiconductor elements are provided. An interlayer insulating film is provided on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a step portion that is in contact with the interlayer insulating film.