公开(公告)号：US20230389299A1

公开(公告)日：2023-11-30

申请号：US18093568

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunjung KIM ,  Sohyun PARK

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/485 ,  H10B12/488 ,  H10B12/482 ,  H01L23/5283

Abstract: A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

公开(公告)号：US20170294440A1

公开(公告)日：2017-10-12

申请号：US15631105

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

公开(公告)号：US20170069633A1

公开(公告)日：2017-03-09

申请号：US15148405

申请日：2016-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

IPC: H01L27/108 ,  H01L21/027 ,  H01L49/02 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/311

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

Abstract translation: 一种形成半导体器件的方法包括在包括蚀刻停止层的基底上形成模制层和支撑层，在支撑层上形成掩模层，在掩模层上形成第一边缘阻挡层，通过 蚀刻掩模层，形成孔，在孔中形成下电极，在载体层上形成支持体掩模层，在载体掩模层上形成第二边缘阻挡层，通过图案化载体掩模层形成载体掩模图案 形成穿过支撑层的支撑件开口，去除模制层，在下电极上形成电容器电介质层和上电极，在上电极上形成层间绝缘层，并平坦化层间绝缘层。 孔穿过支撑层，模制层和蚀刻停止层。