公开(公告)号：US09721967B2

公开(公告)日：2017-08-01

申请号：US15138873

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11578 ,  H01L29/49 ,  H01L23/535 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

公开(公告)号：US09343478B2

公开(公告)日：2016-05-17

申请号：US14486547

申请日：2014-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SunWoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract translation: 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US08865579B2

公开(公告)日：2014-10-21

申请号：US13667618

申请日：2012-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunwoo Lee ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L29/72 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.

Abstract translation: 非易失性存储器件包括三维地布置在半导体衬底上的栅电极，从半导体衬底延伸并与栅电极的侧壁交叉的半导体图案，形成在半导体图案之间并形成在顶表面和底表面上的金属衬垫图案 以及形成在半导体图案和金属衬垫图案之间的电荷存储层。

公开(公告)号：US20130059432A1

公开(公告)日：2013-03-07

申请号：US13667618

申请日：2012-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNWOO LEE ,  Sangwoo Lee ,  Changwon Lee ,  Jeonggil Lee

IPC: H01L21/28 ,  H01L21/20

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L23/535 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1159 ,  H01L29/4958 ,  H01L29/4966

Abstract: A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.