公开(公告)号：US11069768B2

公开(公告)日：2021-07-20

申请号：US16781151

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Lim Park ,  Se Hyoung Ahn ,  Sang Yeol Kang ,  Chang Mu An ,  Kyoo Ho Jung

IPC: H01L27/11507 ,  H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

公开(公告)号：US12094924B2

公开(公告)日：2024-09-17

申请号：US17567316

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoo Ho Jung ,  Sang Yeol Kang ,  Su Hwan Kim ,  Dong Kwan Baek ,  Yu Kyung Shin ,  Won Sik Choi

IPC: G11C11/402 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/65 ,  G11C11/4023 ,  H10B12/30

Abstract: A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).

公开(公告)号：US11527604B2

公开(公告)日：2022-12-13

申请号：US17342610

申请日：2021-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Lim Park ,  Se Hyoung Ahn ,  Sang Yeol Kang ,  Chang Mu An ,  Kyoo Ho Jung

IPC: H01L27/11507 ,  H01L27/108 ,  H01L49/02

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion, the outer portion including first and second regions, and an inner portion inside the outer portion, a dielectric film on the lower electrode to extend along the first region of the outer portion, and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion being different from a concentration of the metal dopant in the second region of the outer portion.

公开(公告)号：US10825889B2

公开(公告)日：2020-11-03

申请号：US16012997

申请日：2018-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Yeol Kang ,  Kyu Ho Cho ,  Han Jin Lim ,  Cheol Seong Hwang

IPC: H01L49/02 ,  H01L27/108

Abstract: A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

公开(公告)号：US20130149833A1

公开(公告)日：2013-06-13

申请号：US13705320

申请日：2012-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hyoung Choi ,  Ki Yeon Park ,  Joon Kim ,  Cha Young Yoo ,  Youn Soo Kim ,  Ho Jun Kwon ,  Sang Yeol Kang

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L28/92

Abstract: A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

Abstract translation: 一种制造半导体器件的方法，所述方法包括：制备包括模层和设置在所述模层上的支撑层的半导体衬底; 形成穿过模层和支撑层的多个孔; 在孔中形成多个底部电极; 通过去除模具层的至少一部分来暴露至少一部分底部电极; 从底部电极的暴露表面去除一部分底部电极; 并且在底部电极上依次形成电介质层和顶部电极层。