公开(公告)号：US20210159121A1

公开(公告)日：2021-05-27

申请号：US16909136

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Jungchul LEE ,  Byungmoon BAE ,  Junggeun SHIN ,  Hyunsu SIM

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/683

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20150079791A1

公开(公告)日：2015-03-19

申请号：US14326960

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjoon PARK ,  Junho YOON ,  Je-Woo HAN ,  Chan-Won KIM

IPC: H01L21/308 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/40 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayered insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayered insulating layer, forming trenches in the first mask layer exposing the interlayered insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayered insulating layer may be greater than that of the key mask patterns with respect to the interlayered insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在具有单元区域和外围电路区域的结构上形成层间绝缘层，在层间绝缘层上形成第一掩模层，在第一掩模层中形成通过图案化第一掩模 并且在沟槽中形成键掩模图案。 第一掩模图案相对于层间绝缘层的蚀刻选择性可以大于关于键层掩模图案相对于层间绝缘层的蚀刻选择性。