公开(公告)号：US20250102748A1

公开(公告)日：2025-03-27

申请号：US18676584

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon KANG ,  Daegon KIM

IPC: G02B6/42 ,  G02B6/43

Abstract: A semiconductor package includes a redistribution layer on a substrate, a semiconductor chip on the redistribution layer, and a stack structure on the redistribution layer and spaced apart from the semiconductor chip in a horizontal direction, wherein the stack structure includes an optical integrated circuit chip, the first optical integrated circuit chip includes a first region adjacent to the semiconductor chip and a second region adjacent to an outer portion of the substrate, and the optical integrated circuit chip defines a first notch and a first groove in the second region, the first groove recessed upwards in a vertical direction from a lower surface of the optical integrated circuit chip, the first groove recessed downwards in the vertical direction from an upper surface of the optical integrated circuit chip.

公开(公告)号：US20250079320A1

公开(公告)日：2025-03-06

申请号：US18590379

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package comprising: a first redistribution substrate; a module structure on the first redistribution substrate; a first molding layer on the first redistribution substrate and extending around the module structure; a second redistribution substrate on the module structure and the first molding layer; and a first vertical connection structure on a side of the module structure and electrically connecting the first redistribution substrate and the second redistribution substrate, wherein the module structure includes: a third redistribution substrate; a fourth redistribution substrate on the third redistribution substrate; a first semiconductor chip between the third redistribution substrate and the fourth redistribution substrate; a second molding layer between the third redistribution substrate and the fourth redistribution substrate and extending around the first semiconductor chip; and a second semiconductor chip on the fourth redistribution substrate, wherein the first semiconductor chip and the second semiconductor chip are electrically connected by the fourth redistribution substrate.

公开(公告)号：US20250157874A1

公开(公告)日：2025-05-15

申请号：US18740039

申请日：2024-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a frame on a redistribution substrate, the frame including an interconnection structure and having a cavity, a first semiconductor chip on the redistribution substrate in the cavity, the first semiconductor chip having a heat dissipation layer on an upper surface thereof, an encapsulation layer having a first portion on the first semiconductor chip, and a second portion on the upper surface of the frame, heat dissipation pads on the first portion, and respectively having a heat dissipation via connected to the heat dissipation layer passing through the encapsulation layer, and including a mark pad having a mark, connection pads on the second portion, and respectively having a connection via connected to the interconnection structure through the encapsulation layer, a second semiconductor chip on the encapsulation layer, and connected to the connection pads, and a heat sink on the heat dissipation pads.

公开(公告)号：US20250140709A1

公开(公告)日：2025-05-01

申请号：US19006392

申请日：2024-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

公开(公告)号：US20250062302A1

公开(公告)日：2025-02-20

申请号：US18605431

申请日：2024-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a lower redistribution substrate, a logic structure on the lower redistribution substrate, connection terminals between the lower redistribution substrate and the logic structure, connection structures on the lower redistribution substrate and surrounding the logic structure in plan view, and external connection terminals below the lower redistribution substrate. The logic structure includes a first redistribution substrate, a connection substrate on the first redistribution substrate and having an opening in the connection substrate, a first logic chip on the first redistribution substrate and in the opening in the connection substrate, and a second logic chip on the connection substrate and the first logic chip. A first active surface of the first logic chip faces a second active surface of the second logic chip.

公开(公告)号：US20250038122A1

公开(公告)日：2025-01-30

申请号：US18596207

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG ,  Seungwan Shin ,  Jung Hyun Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Provided is a semiconductor package including a first redistribution substrate including a first redistribution insulating layer and a first redistribution via, a first insulating layer on the first redistribution substrate, a solder pad on the first insulating layer, a first alignment key penetrating the first insulating layer and extending to an inside of the first redistribution insulating layer, and a solder via spaced apart from the first alignment key and electrically connected to the solder pad, wherein the first alignment key includes a first key body extending from a first surface of the first insulating layer to the inside of the first redistribution substrate, and a first key protrusion protruding from a side surface of the first key body toward the first insulating layer, and wherein the first insulating layer includes a non-photosensitive material.

公开(公告)号：US20220344252A1

公开(公告)日：2022-10-27

申请号：US17527414

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon KANG

IPC: H01L23/498 ,  H01L23/31

Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.