公开(公告)号：US20230013176A1

公开(公告)日：2023-01-19

申请号：US17656011

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon Kim ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

公开(公告)号：US11417597B2

公开(公告)日：2022-08-16

申请号：US17105736

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong-Soo Kim ,  Juhyeon Kim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/31

Abstract: Provided is a semiconductor package including a redistribution substrate, a connection substrate on the redistribution substrate, the connection substrate having an opening that penetrates the connection substrate, a semiconductor chip in the opening of the connection substrate, and a molding layer that covers the semiconductor chip and the connection substrate, and fills a space between the semiconductor chip and the connection substrate, the connection substrate includes a base layer, a plurality of vias that vertically penetrate the base layer, a plurality of first patterns on a top surface of the base layer and connected to the plurality of vias, and a plurality of second patterns on a bottom surface of the base layer and connected to the plurality of vias, an extension of the molding layer extends into a plurality of holes that are spaced apart from the plurality of vias and are formed to vertically penetrate the base layer.