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    MEMORY DEVICE, ELECTRONIC DEVICE, AND OPERATING METHOD OF MEMORY DEVICE FOR VOTING VALID SIGNAL
    12.
    发明公开
    MEMORY DEVICE, ELECTRONIC DEVICE, AND OPERATING METHOD OF MEMORY DEVICE FOR VOTING VALID SIGNAL 审中-公开

    公开(公告)号：US20240249051A1

    公开(公告)日：2024-07-25

    申请号：US18449304

    申请日：2023-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungoh Ahn ,  Jaewon Park

    IPC: G06F30/327

    CPC classification number: G06F30/327

    Abstract: Disclosed is a memory device, which includes a logic circuit that receives a first signal and a second signal from an external host, an output circuit that receives a first logic operation result or a second logic operation result from the logic circuit, a first logic gate that receives the first signal or the second signal and performs a third logic operation to output a third signal, a second logic gate that receives the first signal and the second signal and performs a fourth logic operation to output a fourth signal, and a multiplexer that receives the third signal and the fourth signal, receives the first logic operation result or the second logic operation result from the output circuit, and outputs one of the third signal and the fourth signal as a fifth signal in response to the first or second logic operation results.

    Built-in self-test circuits for memory systems having multiple channels
    16.
    发明授权
    Built-in self-test circuits for memory systems having multiple channels 有权

    公开(公告)号：US12230345B2

    公开(公告)日：2025-02-18

    申请号：US18059462

    申请日：2022-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaewon Park ,  Shinhaeng Kang

    IPC: G11C29/12 ,  G06F11/00 ,  G11C29/28 ,  G11C29/36

    Abstract: A memory system includes a plurality of memory devices having respective arrays of memory cells therein, a bus electrically coupled to and shared by the plurality of memory devices, and a memory controller. The memory controller, which is electrically coupled to the bus, includes a built-in self-test (BIST) circuit, which is commonly connected to the plurality of memory devices. The BIST circuit is configured to transfer a command set including a test pattern to the plurality of memory devices via the bus, and transfer a command trigger signal for driving the test pattern to the plurality of memory devices via the bus.

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