公开(公告)号：US20220223713A1

公开(公告)日：2022-07-14

申请号：US17702856

申请日：2022-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Satoru Yamada ,  Junsoo Kim ,  Honglae Park ,  Chunhyung Chung

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

公开(公告)号：US11296089B2

公开(公告)日：2022-04-05

申请号：US16850223

申请日：2020-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmi Yoon ,  Donghyun Im ,  Jooyub Kim ,  Juhyung We ,  Namhoon Lee ,  Chunhyung Chung

IPC: H01L27/108 ,  H01L21/762 ,  H01L29/06

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.