公开(公告)号：US09830856B2

公开(公告)日：2017-11-28

申请号：US15351358

申请日：2016-11-14

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G06F3/038 ,  G09G5/00 ,  G09G3/3225 ,  G09G3/3266 ,  G11C19/28

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

公开(公告)号：US20170061874A1

公开(公告)日：2017-03-02

申请号：US15351358

申请日：2016-11-14

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。

公开(公告)号：US09294086B2

公开(公告)日：2016-03-22

申请号：US14456995

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd. ,  Industry-University Cooperation Foundation Hanyang-University

Inventor： Oh-Kyong Kwon ,  Yeong-Keun Kwon ,  Jong-Hee Kim ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: H03K3/00 ,  H03K17/687 ,  G09G3/32 ,  G11C19/18 ,  G11C19/28

CPC classification number: H03K17/687 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/184 ,  G11C19/28

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract translation: 舞台电路包括第一驱动器，第二驱动器，第一输出单元和第二输出单元。 第一驱动器根据第一电源，提供给第一输入端的前一级的起始信号或进位信号，提供给第二输入端的第一时钟信号和第二驱动器控制第一和第二节点的电压， 提供给第三输入端的时钟信号。 第二驱动器根据第一电源控制第三节点的电压，提供给第一输入端的先前级的起始信号或进位信号，提供给第四输入端的下一级的进位信号， 和第二节点的电压。

公开(公告)号：US20160042694A1

公开(公告)日：2016-02-11

申请号：US14728844

申请日：2015-06-02

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Hui-Won Yang ,  Chong-Chui Chai

IPC: G09G3/32

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2310/0251 ,  G09G2320/043

Abstract: A pixel circuit and an OLED display including the same are disclosed. The pixel circuit includes a driving transistor having a double gate structure, the driving transistor including a first gate electrode electrically connected to a first node, a second gate electrode electrically connected to a second node, a first electrode electrically connected to a first power supply voltage, and a second electrode electrically connected to the anode of the OLED. The pixel circuit also includes a switching transistor including a gate electrode configured to receive a scan signal, a first electrode configured to receive a data voltage, and a second electrode electrically connected to the first node. The pixel circuit further includes a storage capacitor and a compensation capacitor including a first electrode electrically connected to the second node and a second electrode electrically connected to the first electrode of the driving transistor.

Abstract translation: 公开了包括其的像素电路和OLED显示器。 像素电路包括具有双栅极结构的驱动晶体管，驱动晶体管包括与第一节点电连接的第一栅电极，与第二节点电连接的第二栅电极，电连接到第一电源电压的第一电极 以及与OLED的阳极电连接的第二电极。 像素电路还包括开关晶体管，其包括被配置为接收扫描信号的栅电极，被配置为接收数据电压的第一电极和与第一节点电连接的第二电极。 像素电路还包括存储电容器和包括电连接到第二节点的第一电极和电连接到驱动晶体管的第一电极的第二电极的补偿电容器。

公开(公告)号：US20150206490A1

公开(公告)日：2015-07-23

申请号：US14461359

申请日：2014-08-15

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36 ,  H03K3/012

CPC classification number: G09G3/3677 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/0435

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

Abstract translation: 门驱动电路包括：上拉控制器，响应于前一级之一的进位信号，将先前级之一的进位信号应用于第一节点; 输出时钟信号作为第N栅极输出信号的上拉部分; 输出时钟信号作为第N个进位信号的进位部分; 第一下拉部分，将第一节点处的信号下拉到第二关断电压; 第二下拉部分，将第N栅极输出信号下拉到第一关断电压; 反相部分基于时钟信号和第二截止电压产生反相信号，以将反相信号输出到反相节点; 以及将复位信号输出到反相节点的复位部分。

公开(公告)号：US10455170B2

公开(公告)日：2019-10-22

申请号：US15679800

申请日：2017-08-17

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Eun Park ,  Jin-Woo Noh ,  Young-Wook Yoo ,  Jae-Keun Lim ,  Hassan Kamal

IPC: H04N5/357 ,  G02B27/01 ,  G06T3/40

Abstract: An image processor includes a scaling unit configured to output converted data by resizing first image data; and a rendering unit configured to receive second image data, to output rendering data by rendering the second image data, and to calculate a target rendering data value based on data values corresponding to a first block of M*N among the second image data, where each of M and N is an integer greater than or equal to 2. Here, the second image data is the converted data, or the first image data is the rendering data.

公开(公告)号：US10134352B2

公开(公告)日：2018-11-20

申请号：US15383686

申请日：2016-12-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Ji-Sun Kim ,  Kyoung-Ju Shin ,  Chong-Chul Chai ,  Jong-Hee Kim

IPC: G09G3/36

Abstract: A gate driving circuit includes: a pull-up controller applying a carry signal of one of previous stages to a first node in response to the carry signal of the one of the previous stages; a pull-up part outputting a clock signal as an N-th gate output signal; a carry part outputting the clock signal as an N-th carry signal; a first pull-down part pulling down the signal at the first node to a second off voltage; a second pull-down part pulling down the N-th gate output signal to a first off voltage; an inverting part generating an inverting signal based on the clock signal and the second off voltage to output the inverting signal to an inverting node; and a reset part outputting a reset signal to the inverting node.

公开(公告)号：US10078011B2

公开(公告)日：2018-09-18

申请号：US15623045

申请日：2017-06-14

Applicant: Samsung Display Co., LTD.

Inventor： Joon-Chul Goh ,  Jae-Keun Lim

IPC: G06F3/038 ,  G01J1/46 ,  G06F3/041 ,  H01L27/32 ,  G01J1/44

CPC classification number: G01J1/46 ,  G01J2001/444 ,  G01J2001/4473 ,  G06F3/0412 ,  H01L27/3227 ,  H01L27/3234

Abstract: A light sensitive circuit includes a light sensing capacitor and a driving transistor. The light sensing capacitor is configured to sense light of a predetermined one or more wavelengths. The driving transistor includes a gate electrode electrically connected to the light sensing capacitor and is configured to generate a light sensing current according to a voltage of the gate electrode in the driving transistor. A light sensing accuracy and a light sensing signal to noise ratio (SNR) of the display apparatus including a plurality of such light sensing capacitors may be improved relative to ones that do not include such light sensing capacitors.

公开(公告)号：US20160104424A1

公开(公告)日：2016-04-14

申请号：US14663143

申请日：2015-03-19

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Keun Lim ,  Chong-Chul Chai ,  Joon-Chul Goh ,  Mu-Kyung Jeon

IPC: G09G3/32 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G2300/0852 ,  G09G2310/0262 ,  G09G2310/0278 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78648

Abstract: A pixel, a display device having the same, and a thin film transistor (TFT) substrate for the display device are disclosed. In one aspect, the pixel includes an emitter configured to emit light based at least in part on a driving current. The pixel also includes a driving transistor including an active layer, a first electrode electrically connected to a first end portion of the active layer, a second electrode electrically connected to a second end portion of the active layer, a first gate electrode configured to receive a data voltage from a data driver so as to form a channel in the active layer, and a second gate electrode configured to receive a bias voltage from a voltage source, wherein the channel is configured to adjust the driving current.

Abstract translation: 公开了一种像素，具有该像素的显示装置和用于显示装置的薄膜晶体管（TFT）基板。 在一个方面，像素包括被配置为至少部分地基于驱动电流发光的发射器。 该像素还包括驱动晶体管，其包括有源层，与有源层的第一端部电连接的第一电极，与该有源层的第二端部电连接的第二电极，被配置为接收 来自数据驱动器的数据电压，以便在有源层中形成通道;以及第二栅电极，被配置为从电压源接收偏置电压，其中该通道被配置为调节驱动电流。

公开(公告)号：US09293093B2

公开(公告)日：2016-03-22

申请号：US14231001

申请日：2014-03-31

Applicant: Samsung Display Co., LTD.

Inventor： Jong-Hee Kim ,  Yeong-Keun Kwon ,  Ji-Sun Kim ,  Jae-Keun Lim ,  Chong-Chul Chai

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/08

Abstract: A gate driver circuit includes an N-th stage (‘N’ is a natural number) The N-th stage (‘N’ is a natural number) includes a pull-up part configured to output an N-th gate signal using a first clock signal in response to a node signal of the control node, a carry part configured to output an N-th carry signal using the first clock signal in response to the node signal of the control node, an first output part connected to an n-th gate line and configured to output an n-th gate signal using the N-th gate signal in response to a second clock signal having a period shorter than the first clock signal (‘n’ is a natural number), and a second output part connected to an (n+1)-th gate line and configured to output an (n+1)-th gate signal using the N-th gate signal in response to an second inversion clock signal having a phase opposite to the second clock signal.

Abstract translation: 栅极驱动器电路包括第N级（“N”是自然数）第N级（“N”是自然数）包括被配置为使用第n级输出第N门信号的上拉部分 响应于所述控制节点的节点信号的第一时钟信号，被配置为响应于所述控制节点的节点信号而使用所述第一时钟信号输出第N进位信号的进位部分，连接到所述控制节点的第一输出部分 并且被配置为响应于具有比第一时钟信号（'n'是自然数）短的周期的第二时钟信号，使用第N个门信号输出第n个门信号，第二 输出部分连接到第（n + 1）栅极线，并被配置为响应于具有与第二栅极相反相位的第二反相时钟信号，使用第N栅极信号输出第（n + 1）栅极信号 时钟信号。